Intel
®
Xeon
®
E3-1125C v2, E3-1105C v2,
Intel
®
Pentium
®
Processor B925C, and
Intel
®
Core™ i3-3115C Processors for
Communications Infrastructure
- Volume 1 of 2
Supporting:
Intel
®
Xeon
®
Processor E3-1125C v2
Intel
®
Xeon
®
Processor E3-1105C v2
Intel
®
Core™ Processor i3-3115C
Intel
®
Pentium
®
Processor B925C
Mobile/Desktop 3rd Generation Intel
®
Core™ Processor Family Datasheet, Volume 2,
completes the documentation set and contains additional product information.
November 2013
Order Number: 329374-002US
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®
Pentium
®
4 processor supporting HT Technology and a HT Technology enabled
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Copyright © 2013, Intel Corporation. All Rights Reserved.
Intel
®
Xeon
®
E3-1125C v2, E3-1105C v2, Intel
®
Pentium
®
Processor B925C, and Intel
®
Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
November 2013
2
Order Number: 329374-002US
Contents—Intel
®
Xeon
®
and Intel
®
Core™ Processors for Communications Infrastructure
Contents
1.0
Introduction
............................................................................................................ 10
1.1
Purpose / Scope / Audience ................................................................................ 10
1.2
Related Documents ........................................................................................... 10
1.3
Terminology ..................................................................................................... 12
Product Overview
.................................................................................................... 14
2.1
Processor Feature Details ................................................................................... 16
2.1.1 Supported Technologies .......................................................................... 16
2.2
Interface Features ............................................................................................. 16
2.2.1 System Memory Support ......................................................................... 16
2.2.2 PCI Express* ......................................................................................... 17
2.2.3 Direct Media Interface (DMI).................................................................... 19
2.2.4 Platform Environment Control Interface (PECI) ........................................... 20
2.3
Power Management Support ............................................................................... 20
2.3.1 Processor Core....................................................................................... 20
2.3.2 System ................................................................................................. 20
2.3.3 Memory Controller.................................................................................. 20
2.3.4 PCI Express* ......................................................................................... 20
2.3.5 DMI...................................................................................................... 20
2.4
Thermal Management Support ............................................................................ 20
2.5
Package ........................................................................................................... 21
2.6
Processor Compatibility ...................................................................................... 21
Interfaces................................................................................................................
22
3.1
System Memory Interface .................................................................................. 22
3.1.1 System Memory Configurations Supported................................................. 22
3.1.2 System Memory Timing Support............................................................... 25
3.1.3 System Memory Organization Modes......................................................... 26
3.1.4 Rules for Populating Memory Slots ............................................................ 27
3.1.5 Technology Enhancements of Intel
®
Fast Memory Access (Intel
®
FMA).......... 27
3.1.6 Data Scrambling .................................................................................... 28
3.1.7 DRAM Clock Generation........................................................................... 28
3.1.8 DDR3 Reference Voltage Generation ......................................................... 28
3.2
PCI Express* Interface....................................................................................... 29
3.2.1 PCI Express* Architecture ....................................................................... 29
3.2.2 PCI Express* Configuration Mechanism ..................................................... 31
3.2.3 PCI Express* Port Bifurcation................................................................... 32
3.2.4 PCI Express* Lanes Connection ................................................................ 34
3.2.5 Configuring PCIe* Lanes ......................................................................... 35
3.2.6 Lane Reversal on PCIe* Interface ............................................................. 36
3.3
Direct Media Interface........................................................................................ 36
3.3.1 DMI Error Flow....................................................................................... 36
3.3.2 DMI Link Down ...................................................................................... 36
3.4
Platform Environment Control Interface (PECI) ...................................................... 36
3.5
Interface Clocking ............................................................................................. 37
3.5.1 Internal Clocking Requirements................................................................ 37
Technologies
........................................................................................................... 39
4.1
Intel
®
Virtualization Technology .......................................................................... 39
4.1.1 Intel
®
VT-x Objectives ............................................................................ 39
4.1.2 Intel
®
VT-x Features .............................................................................. 39
4.1.3 Intel
®
VT-d Objectives ............................................................................ 40
4.1.4 Intel
®
VT-d Features .............................................................................. 40
2.0
3.0
4.0
Intel
®
Xeon
®
E3-1125C v2, E3-1105C v2, Intel
®
Pentium
®
Processor B925C, and Intel
®
Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
Order Number: 329374-002US
3
Intel
®
Xeon
®
and Intel
®
Core™ Processors for Communications Infrastructure—Contents
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5.0
6.0
4.1.5 Intel
®
VT-d Features Not Supported..........................................................41
Intel
®
Trusted Execution Technology (Intel
®
TXT) .................................................41
Intel
®
Hyper-Threading Technology .....................................................................42
Intel
®
Advanced Vector Extensions (Intel
®
AVX)....................................................42
Intel
®
Advanced Encryption Standard New Instructions (Intel
®
AES-NI) ...................42
4.5.1 PCLMULQDQ Instruction ..........................................................................42
4.5.2 RDRAND Instruction ................................................................................43
Intel
®
64 Architecture x2APIC .............................................................................43
Supervisor Mode Execution Protection (SMEP) .......................................................44
Power Aware Interrupt Routing (PAIR)..................................................................44
Processor SKUs
........................................................................................................45
5.1
SKU Features ....................................................................................................45
Power Management
.................................................................................................46
6.1
ACPI States Supported .......................................................................................47
6.1.1 System States........................................................................................47
6.1.2 Processor Core/Package Idle States...........................................................47
6.1.3 Integrated Memory Controller States .........................................................47
6.1.4 PCIe* Link States ...................................................................................48
6.1.5 DMI States ............................................................................................48
6.1.6 Interface State Combinations ...................................................................48
6.2
Processor Core Power Management ......................................................................49
6.2.1 Enhanced Intel SpeedStep® Technology ....................................................49
6.2.2 Low-Power Idle States.............................................................................49
6.2.3 Requesting Low-Power Idle States ............................................................51
6.2.4 Core C-States ........................................................................................51
6.2.5 Package C-States ...................................................................................53
6.3
IMC Power Management .....................................................................................55
6.3.1 Disabling Unused System Memory Outputs.................................................56
6.3.2 DRAM Power Management and Initialization ...............................................56
6.3.3 DDR Electrical Power Gating (EPG) ............................................................59
6.4
PCIe* Power Management ..................................................................................59
6.5
DMI Power Management .....................................................................................59
6.6
Intel® Rapid Memory Power Management (RMPM) (Also Known as CxSR) .................59
6.7
Thermal Power Management ...............................................................................59
Thermal Management
..............................................................................................61
7.1
Thermal Considerations ......................................................................................61
7.2
Thermal and Power Specifications ........................................................................62
7.3
Thermal Management Features............................................................................63
7.3.1 Adaptive Thermal Monitor ........................................................................63
7.3.2 Processor Core Specific Thermal Features ..................................................68
7.3.3 Memory Controller Specific Thermal Features .............................................68
7.3.4 Memory Thermal Management..................................................................68
7.3.5 Platform Environment Control Interface (PECI) ...........................................69
Signal Description
....................................................................................................70
8.1
System Memory Interface ...................................................................................71
8.2
Memory Reference and Compensation ..................................................................73
8.3
Reset and Miscellaneous Signals ..........................................................................74
8.4
PCI Express* Based Interface Signals ...................................................................75
8.5
DMI .................................................................................................................75
8.6
PLL Signals .......................................................................................................75
8.7
TAP Signals.......................................................................................................76
8.8
Error and Thermal Protection...............................................................................77
7.0
8.0
Intel
®
Xeon
®
E3-1125C v2, E3-1105C v2, Intel
®
Pentium
®
Processor B925C, and Intel
®
Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
November 2013
4
Order Number: 329374-002US
Contents—Intel
®
Xeon
®
and Intel
®
Core™ Processors for Communications Infrastructure
8.9
8.10
8.11
8.12
9.0
Power Sequencing ............................................................................................. 78
Processor Power and Ground Signals.................................................................... 78
Sense Pins ....................................................................................................... 79
Processor Internal Pull Up/Pull Down.................................................................... 79
Electrical Specifications
........................................................................................... 80
9.1
Power and Ground Pins ...................................................................................... 80
9.2
Decoupling Guidelines ........................................................................................ 80
9.2.1 Voltage Rail Decoupling........................................................................... 80
9.3
Processor Clocking (BCLK, BCLK#) ...................................................................... 81
9.3.1 PLL Power Supply ................................................................................... 81
9.4
Serial Voltage Identification (SVID)...................................................................... 81
9.5
System Agent (SA) Vcc VID ................................................................................ 88
9.6
Reserved or Unused Signals................................................................................ 89
9.7
Signal Groups ................................................................................................... 89
9.8
Test Access Port (TAP) Connection....................................................................... 91
9.9
Storage Conditions Specifications ........................................................................ 91
9.10 DC Specifications .............................................................................................. 92
9.10.1 Voltage and Current Specifications............................................................ 92
9.10.2 Platform Environmental Control Interface DC Specifications ......................... 99
10.0 Processor Ball and Package Information
............................................................... 101
10.1 Processor Ball Assignments............................................................................... 101
10.2 Package Mechanical Information........................................................................ 128
11.0 Processor Configuration Registers
......................................................................... 130
11.1 ERRSTS - Error Status ..................................................................................... 131
11.2 ERRCMD - Error Command ............................................................................... 132
11.3 SMICMD - SMI Command ................................................................................. 132
11.4 SCICMD - SCI Command .................................................................................. 133
11.5 ECCERRLOG0_C0 - ECC Error Log 0 ................................................................... 133
11.6 ECCERRLOG1_C0 - ECC Error Log 1 ................................................................... 135
11.7 ECCERRLOG0_C1 - ECC Error Log 0 ................................................................... 135
11.8 ECCERRLOG1_C1 - ECC Error Log 1 ................................................................... 136
11.9 MAD_DIMM_CH0 - Address Decode Channel 0..................................................... 136
11.10 MAD_DIMM_CH1 - Address Decode Channel 1..................................................... 138
11.11 Error Detection and Correction .......................................................................... 138
Figures
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
6-1
6-2
6-3
6-4
7-1
9-1
Platform Example Block Diagram .......................................................................... 15
Processor Compatibility Diagram .......................................................................... 21
Intel® Flex Memory Technology Operation ............................................................ 27
PCI Express* Layering Diagram............................................................................ 30
Packet Flow through the Layers............................................................................ 30
PCI Express* Related Register Structures .............................................................. 32
PCI Express* PCI Port Bifurcation ......................................................................... 33
PCIe* Typical Operation 16 Lanes Mapping ............................................................ 34
Power States ..................................................................................................... 46
Idle Power Management Breakdown of the Processor Cores ..................................... 50
Thread and Core C-State Entry and Exit ................................................................ 50
Package C-State Entry and Exit ............................................................................ 54
Frequency and Voltage Ordering........................................................................... 64
Example of PECI Host-Client Connection................................................................ 99
Intel
®
Xeon
®
E3-1125C v2, E3-1105C v2, Intel
®
Pentium
®
Processor B925C, and Intel
®
Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
Order Number: 329374-002US
5
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