19-1291; Rev 0; 9/97
IF Undersampler
_______________General Description
The MAX1005 is a combined digitizer and reconstruc-
tion integrated circuit designed to work in systems that
demodulate and modulate communications signals. It
integrates IF undersampling and signal synthesis func-
tions into a single, low-power circuit. Its analog-to-
digital converter (ADC) is used to directly sample or
undersample a downconverted RF signal, while its
digital-to-analog converter (DAC) recreates the IF sub-
carrier and transmission data. The MAX1005’s ADC is
ideal for undersampling applications, due to the analog
input amplifier’s wide (15MHz) bandwidth. The DAC
has very low glitch energy, which minimizes the trans-
mission of unwanted spurious signals. An on-chip
reference provides for low-noise ADC and DAC conver-
sions.
The MAX1005 provides a high level of signal integrity
from a low power budget. It operates from a single
power supply, or from separate analog and digital sup-
plies with independent voltages ranging from +2.7V to
+5.5V. The MAX1005 can operate with an unregulated
analog supply of 5.5V and a regulated digital supply
down to 2.7V. This flexible power-supply operation
saves additional power in complex digital systems.
The MAX1005 has three operating modes: transmit
(DAC active), receive (ADC active), and shutdown
(ADC and DAC inactive). In shutdown mode, the total
supply current drops below 1µA. The device requires
only 2.4µs to wake up from shutdown mode. The
MAX1005 is ideal for hand-held, as well as base-station
applications. It is available in a tiny 16-pin QSOP pack-
age specified for operation over both the commercial
and extended temperature ranges.
____________________________Features
o
Differential-Input, 5-Bit ADC
o
Differential-Output, 7-Bit DAC
o
15Msps Min Conversion Rate
o
25MHz -1dB Full-Power Bandwidth
o
44dB SFDR for ADC
39dB at 10.7MHz SFDR (Imaged) for DAC
o
Internal Voltage Reference
o
Parallel Logic Interface
o
Single-Supply Operation (+2.7V to +5.5V)
o
0.1µA Low-Power Shutdown Mode
MAX1005
______________Ordering Information
PART
MAX1005CEE
MAX1005EEE
TEMP. RANGE
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
16 QSOP
16 QSOP
__________________Pin Configuration
TOP VIEW
VCCD 1
16 CLK
15 D0
14 D1
________________________Applications
PWT1900
PHS/P
Wireless Loops
PCS/N
DGND 2
RXEN 3
AIO+ 4
AIO- 5
TXEN 6
AGND 7
VCCA 8
MAX1005
13 D2
12 D3
11 D4
10 D5
9
D6
QSOP
Functional Diagram appears at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
IF Undersampler
MAX1005
ABSOLUTE MAXIMUM RATINGS
VCCA to AGND ........................................................-0.3V, +6.0V
VCCD to DGND ........................................................-0.3V, +6.0V
VCCA to VCCD ...................................................................±6.3V
Digital I/O Pins (D0–D6, CLK, RXEN, TXEN)
to DGND .................................-0.3V to (VCCD + 0.3V) or 6.0V
(whichever is smaller)
Analog I/O Pins (AIO+, AIO-)
to AGND................................(VCCA - 1.5V) to (VCCA + 0.3V)
AGND to DGND........................................................-0.3V, +0.3V
Power Dissipation (T
A
= +70°C)
QSOP (derate 5.90mW/°C above 70°C) ......................470mW
Operating Temperature Ranges
MAX1005CEE .....................................................0°C to +70°C
MAX1005EEE...................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, <10sec)...........................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCCA = VCCD = 3.0V, f
CLK
= 15MHz, R
L
=
∞,
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Transmit Full-Scale Output Voltage
V
OUT
VCCA = VCCD = 3.0V
VCCA = VCCD = 2.7V to 5.5V
VCCA = VCCD = 3.0V
0.7
(Note 5)
(Notes 6, 7)
PSR
VCC_ (A or D or both) = 3.0V ±100mVp-p at
100kHz
5
±0.2
±0.2
AIO+ = AIO-
V
IN
VCCA = VCCD = 3.0V
VCCA = VCCD = 2.7V to 5.5V
VCCA = VCCD = 3.0V
VCCA = VCCD = 2.7V to 5.5V
VCCA = VCCD = 3.0V
VCCA = VCCD = 2.7V to 5.5V
4.5
24
368
±2
400
-42
-42
44
44
4.9
4.9
432
-24
67
-50
0.5
736
28
800
39
39
-28
2.4
TRANSMIT DAC DYNAMIC PERFORMANCE
(T
A
= +25°C) (Note 2)
Spurious-Free Dynamic Range
Total Harmonic Distortion plus
Noise
Wakeup Time Exiting Shutdown
Clock Feedthrough
DAC Latency
Power-Supply Rejection
SFDR
THD+N
t
WAKE
(Note 3)
(Note 4)
dBc
dBc
µs
dBc
CLK
period
dB
SYMBOL
N
INL
DNL
CONDITIONS
MIN
7
±0.2
±0.2
±1
±1
±1
864
TYP
MAX
UNITS
Bits
LSB
LSB
LSB
mVp-p
TRANSMIT DAC DC ACCURACY
(Note 1)
TRANSMIT ADC DC ACCURACY
(Note 8)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Full-Scale Input Range
N
INL
DNL
Bits
LSB
LSB
LSB
mV
RECEIVE ADC DYNAMIC PERFORMANCE
(T
A
= +25°C) (Note 8)
Total Harmonic Distortion
Spurious-Free Dynamic Range
Effective Number of Bits
THD
SFDR
ENOB
(Notes 9, 10)
(Note 9)
(Note 9)
dB
dB
Bits
2
_______________________________________________________________________________________
IF Undersampler
ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCD = 3.0V, f
CLK
= 15MHz, R
L
=
∞,
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
Input Full-Power Bandwidth
(-1dB)
Conversion Rate
Wakeup Time Exiting Shutdown
Mode
Power-Supply Rejection
t
WAKE
PSR
VCC_ (A or D or both) = 3.0V ±100mVp-p at
100kHz
SYMBOL
CONDITIONS
V
IN
= 90% of full scale
MIN
15
15
0.6
<0.1
2.4
TYP
25
MAX
UNITS
MHz
Msps
µs
LSB
MAX1005
ANALOG INPUT/OUTPUT (AIO+, AIO-)
(Note 11)
Input Resistance
Input Resistance Temperature
Coefficient
Input Capacitance (Note 6)
POWER REQUIREMENTS
Supply Voltage
VCCA,
VCCD
RXEN = 1, TXEN = 0,
VCCA = VCCD ADC on, DAC off
= 3.0V,
RXEN = 0, TXEN = 1,
C
L
≤
12.5pF
ADC off, DAC on
RXEN = 1, TXEN = 0,
VCCA = VCCD ADC on, DAC off
= 3.0V,
RXEN = 0, TXEN = 1,
C
L
≤
12.5pF
ADC off, DAC on
VCCA = VCCD = 3.0V, C
L
≤
12.5pF,
RXEN = TXEN
2.7
9.0
2.5
4.0
3.0
<0.1
5.5
14.8
mA
3.8
6.4
mA
5.6
5
µA
V
R
IN
TCR
IN
C
IN
Differential between AIO+ and AIO-
AIO+ or AIO- to GND
T
A
= +25°C, differential between AIO+ and
AIO-
1.56
2.00
-2000
4
4
2.44
kΩ
ppm/°C
pF
Analog Supply Current
ICCA
Digital Supply Current
ICCD
Shutdown Supply Current
ICCA +
ICD
DIGITAL INPUTS/OUTPUTS (D0–D6, RXEN, TXEN, CLK)
(Note 12)
Output High Voltage
Output Low Voltage
Input High Voltage
V
OH
V
OL
V
IH
D0–D4, VCCD = 2.7V to 5.5V,
I
SOURCE
= 200µA
D0–D4, VCCD = 2.7V to 5.5V, I
SINK
= 50µA
D0–D6, CLK
VCCD = 2.7V
to 5.5V
VCCD = 2.7V
to 5.5V
RXEN, TXEN
D0–D6, CLK
RXEN, TXEN
-0.1
VCCD - 1.0
0
0.7VCCD
VCCD -
0.5
VCCD +
0.1
0.3VCCD
0.5
V
VCCD
0.5
V
V
Input Low Voltage
V
IL
V
_______________________________________________________________________________________
3
IF Undersampler
MAX1005
ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCD = 3.0V, f
CLK
= 15MHz, R
L
=
∞,
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
SYMBOL
RXEN, TXEN;
VCCD = 2.7V
to 3.6V
RXEN, TXEN;
VCCD = 3.6V
to 5.5V
Input Capacitance
DAC Data Setup Time
DAC Data Hold Time
CLK Duty Cycle
ADC CLK to Output Data Valid
Note 1:
t
DO
C
L
≤
12.5pF
C
IN
t
DS
t
HOLD
CONDITIONS
CONDITIONS
D0–D6, CLK; VCCD = 2.7V to 5.5V
TXEN = RXEN
TXEN = 0 and RXEN = 1, or
TXEN = 1 and RXEN = 0
TXEN = RXEN
TXEN = 0 and RXEN = 1, or
TXEN = 1 and RXEN = 0
MIN
-1
TYP
MAX
7
±1
±2
±1
±4
8
5
5
45
13
0.6
0.3
55
20
pF
ns
ns
%
ns
µA
UNITS
Input Current
I
IN
D0–D6, CLK; TXEN = 1, RXEN = 0 (Note 6)
T
A
= +25°C (Note 6)
T
A
= +25°C (Note 6)
TIMING CHARACTERISTICS
(Data Outputs: R
L
= 1MΩ, C
L
= 15pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 12)
TXEN = 1, RXEN = 0. All DAC transfer function parameters are measured differentially from AIO+ to AIO- using the End-
Point Linearity method.
Note 2:
f
IN
= 4.3MHz digital sine wave applied to DAC data inputs; f
CLK
= 15MHz. The reference frequency (f
REF
) is defined to be
10.7MHz (f
CLK
- f
IN
). All frequency components present in the DAC output waveform except for f
REF
and f
IN
are consid-
ered spurious.
Note 3:
For DAC SFDR measurements, the amplitude of f
REF
(10.7MHz) is compared to the amplitudes of all frequency compo-
nents of the output waveform except for f
IN
(4.3MHz).
Note 4:
For DAC measurements, THD+N is defined as the ratio of the square-root of the sum-of-the-squares of the RMS values of
all harmonic and noise components of the output waveform (except for f
IN
and f
REF
) to the RMS amplitude of the f
REF
com-
ponent.
Note 5:
Clock feedthrough is defined as the difference in amplitude between the f
REF
component and the f
CLK
component when
measured differentially from AIO+ to AIO-.
Note 6:
Guaranteed by design. Not production tested.
Note 7:
The DAC input interface is a master/slave register. An additional half clock cycle is required for data at the digital inputs to
propagate through to the DAC switches.
Note 8:
RXEN = 1, TXEN = 0. Unless otherwise noted, for all receive ADC measurements, the analog input signal is applied differ-
entially from AIO+ to AIO-, specified using the Best-Fit Straight-Line Linearity method.
Note 9:
f
IN
= 10.7MHz, f
CLK
= 15MHz. Amplitude is 1dB below full-scale. The reference frequency (f
REF
) is defined to be 4.3MHz
(f
CLK
- f
IN
). All components except for f
REF
and f
IN
are considered spurious.
Note 10:
Receive ADC THD measurements include the first five harmonics.
Note 11:
CAUTION: Operation of the analog inputs AIO+ and AIO- (pins 4 and 5) at more than 1.5V below VCCA could cause
latchup and possible destruction of the part. Avoid shunt capacitances to GND on these pins. If shunt capacitances are
required, then bypass these pins only to VCCA.
Note 12:
All digital input signals are measured from 50% amplitude reference points. All digital output signal propagation delays are
measured to V
OH(AC)
for rising output signals and to V
OL(AC)
for falling output signals. The values for V
OH(AC)
and V
OL(AC)
as a function of the VCCD supply are shown in the following table:
VCCD (V)
2.7 to 3.3
3.3 to 5.5
V
OH(AC)
(V)
VCCD - 1.1
2/3 x VCCD
V
OL(AC)
(V)
0.5
0.5
4
_______________________________________________________________________________________
IF Undersampler
__________________________________________Typical Operating Characteristics
(VCCA = VCCD = 3.0V, T
A
= +25°C, unless otherwise noted.)
MAX1005
RECEIVE ADC
INTEGRAL NONLINEARITY
MAX1005-01
RECEIVE ADC
DIFFERENTIAL NONLINEARITY
MAX1005-02
TRANSMIT DAC
INTEGRAL NONLINEARITY
0.4
0.3
0.2
INL (LSB)
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
MAX1005-03
0.50
0.40
0.30
0.20
0.50
0.40
0.30
0.20
DNL (LSB)
0.10
0.00
-0.10
-0.20
-0.30
-0.40
-0.50
0.5
INL (LSB)
0.10
0.00
-0.10
-0.20
-0.30
-0.40
-0.50
-15 -12 -9
-6
-3
0
CODE
3
6
9
12 15
-15 -12 -9
-6
-3
0
CODE
3
6
9
12 15
-64
-48
-32
-16
0
CODE
16
32
48
64
TRANSMIT DAC
DIFFERENTIAL NONLINEARITY
MAX1005-04
RECEIVE ADC FFT PLOT
MAX1005-05
FULL POWER ANALOG
INPUT BANDWIDTH
V
IN
= 90% OF FULL SCALE
MAX1005-06
0.5
0.4
0.3
30
20
10
AMPLITUDE (dB)
0
-10
-20
-30
-40
-50
-60
-70
f
IN
= 10.7MHz
f
CLK
= 15MHz
256 POINTS
0
-1
-2
-3
-4
-5
-6
-7
DNL (LSB)
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-64
-48
-32
-16
0
CODE
16
32
48
64
0
1.465
2.930
4.395
5.860
7.325
AMPLITUDE (dB)
0.2
1
10
ANALOG INPUT FREQUENCY (MHz)
100
FREQUENCY (MHz)
_______________________________________________________________________________________
5
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