Supertex inc.
Eight Channel, High Speed, Unipolar,
Ultrasound Pulser 1.5A 150V
Features
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HVCMOS technology for high performance
High density integrated ultrasound transmitter
0 to +150V output voltage
±1.5A source and sink current (min.)
±300mA current in CW mode
Up to 18MHz operating frequency
Matched delay times
Built-in gate driver floating voltage regulator
2.5 to 3.3V CMOS logic interface
HV7355
General Description
The Supertex HV7355 is an eight-channel, unipolar, high voltage,
high-speed pulse generator. It is designed for medical ultrasound
applications. This high voltage and high speed integrated circuit can
also be used for other piezoelectric, capacitive or MEMS sensors in
ultrasonic nondestructive detection and sonar ranger applications.
The HV7355 consists of a controller logic interface circuit, level
translators, MOSFET gate drivers and high current P-channel and
N-channel MOSFETs as the output stage for each channel.
The output stages of each channel are designed to provide peak
output currents over ±1.5A for pulsing, when MC = 1, with up to 150V
swings. When MC = 0, all the output stages drop the peak current
to ±500mA for low-voltage CW mode operation to save power. This
direct coupling topology of the gate driver not only saves one high
voltage capacitor per channel, but also makes the PCB layout easier.
Application
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Portable medical ultrasound imaging
Piezoelectric transducer drivers
NDT ultrasound transmission
Pulse waveform generator
Typical Application Circuit
+3.3V
+5.0V
+5.0 to 150V
VLL
AVDD
VDD
LR
VSS
CPF
VPF
VPP
EN
MC
IN0
PWR
VDD
VPP
CWD
LT
VPF
Q0
VDD
VDD
TX0
X0
LT
+3.3V
Logic
RGND
VDD
VPP
VPP
LT
IN7
Q7
Q[7:0]
VDD
VPF
VDD
TX7
X7
SET
LE
CS
SCK
SDO
Data Latch
Shift Reg.
Q7
D0
LT
RGND
SUB
RGND
SDI
VSUB
GND
VSS
-5.0V
Doc.# DSFP-HV7355
D011314
Supertex inc.
www.supertex.com
HV7355
Ordering Information
Part Number
HV7355K6-G
HV7355K6-G M937
Package Options
56-Lead QFN (8x8)
56-Lead QFN (8x8)
Packing
250/Tray
2000/Reel
ESD Sensitive Device
-G denotes a lead (Pb)-free / RoHS compliant package
Pin Configuration
56
Absolute Maximum Ratings
Parameter
V
LL
, Positive logic supply
GND, RGND and V
SUB
Value
0V
-0.5V to +7.0V
-0.5V to +7.0V
+0.5V to -7.0V
-0.5V to +160V
-0.5V to +160V
-0.5V to +160V
-0.5V to +7.0V
-40°C to 125°C
-65°C to 150°C
1
V
DD
, Positive logic and level translator supply
V
PP
, High voltage positive supply
(V
TXx
- RGND) Voltage
( V
PP
-V
TXx
) Voltage
V
SS
, Negative level translator and LR supply
56-Lead QFN
(top view)
Operating temperature
Storage temperature
All logic input PIN
X
, NIN
X
and EN voltages
Package Marking
HV7355K6
LLLLLLLLL
YYWW
AAA CCC
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
Typical Thermal Resistance
Package
56-Lead QFN
θ
ja
21
O
C/W
L = Lot Number
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
= “Green” Packaging
Package may or may not include the following marks: Si or
56-Lead QFN
Power-Up Sequence
Step
1
2
3
4
5
Description
V
SS
V
LL
with logic signal low
V
DD
V
PP
EN & logic signal go to high
Power-Down Sequence
Step
1
3
4
5
6
Description
EN & logic signal low
V
PP
V
DD
V
LL
V
SS
Note:
Powering up/down in any arbitrary sequence will not cause any damage to the device. The powering up/down sequence is only recommended in
order to minimize possible inrush current.
Truth Table
(MC = X)
Logic Inputs
EN
1
1
1
0
Doc.# DSFP-HV7355
D011314
Drive Mode Control Table
Output
IN0~7
0
1
X
X
TX0~7
GND
VPP
GND
HiZ
MC
0
1
(A)
Q[7:0]
1111,1111
1111,1111
0
X
I
SC
R
onP
18
8.0
R
onN
13
3.0
0.50
1.6
Note:
V
PP
= +150V, V
DD
= +5.0 V, V
LL
= +3.3V, V
SS
= -5.0V, V
SUB
= 0V
2
Supertex inc.
www.supertex.com
HV7355
Operating Supply Voltages and Current (Eight Active Channels)
Sym
V
LL
V
DD
V
PP
V
SS
V
PF
I
LL
I
DDQ
I
DDEN
I
DDEN
I
DDENCW
I
SSQ
I
SSEN
I
SSEN
I
SSENCW
I
PPQ
I
PPEN
I
PPEN
I
PPENCW
Parameter
Logic voltage reference
Internal voltage supply
Positive gate driver supply
Negative low voltage supply
Gate driver floating voltage
V
LL
Current EN = Low
V
DD
Current EN = Low
V
DD
Current EN = High
V
DD
Current MC = High
V
DD
Current MC = Low
V
SS
Current EN = Low
V
SS
Current EN = High
V
SS
Current MC = High
V
SS
Current MC = Low
V
PP
Current EN = Low
V
PP
Current EN = High
V
PP
Current MC = High
V
PP
Current MC = Low
Min
2.37
4.5
V
DD
-5.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ
3.30
5.0
-
-5.0
5.0
2.0
50
1.0
160
12
5.0
1.0
95
50
2.0
200
370
300
Max
3.47
5.5
+150
-4.5
-
10
150
4.0
-
-
20
4.0
-
-
10
450
-
-
V
V
V
V
V
μA
μA
mA
mA
mA
μA
mA
mA
mA
μA
μA
mA
mA
---
---
---
---
---
---
f = 0MHz
f = 0MHz
f = 5.0MHz, continuous
no loads
---
f = 0MHz
f = 5.0MHz, continuous
no loads
---
f = 0MHz
f = 5.0MHz, continuous
no loads
(Operating conditions, unless otherwise specified, V
LL
= +3.3V, V
ADD
= V
DD
= +5.0V, V
SS
= -5.0V ,V
PP
= +150V, T
A
= 25°C)
Units Conditions
Under Voltage and Over Temperature Protection
Sym
V
UVDD
V
UVLL
V
UVPF
Parameter
V
DD
threshold
V
LL
threshold
V
PP
- V
PF
threshold
Min
3.4
-
2.5
Typ
-
1.7
-
Max
4.4
-
3.8
Units Conditions
V
V
V
(Internal only)
(Internal only)
(Internal only)
Logic Inputs
Sym
V
IH
V
IL
I
IH
I
IL
C
IN
(Operating conditions, unless otherwise specified, V
LL
= +3.3V, V
ADD
= V
DD
= +5.0V, V
SS
= -5.0V ,V
PP
= +150V, T
A
= 25°C)
Parameter
Input logic high voltage
Input logic low voltage
Input logic high current
Input logic low current
Input logic capacitance
Min
(V
LL
- 0.4)
0
-
-1.0
-
Typ
-
-
-
-
-
Max
V
LL
0.4
1.0
-
5.0
Units Conditions
V
V
μA
μA
pF
---
---
---
---
---
Doc.# DSFP-HV7355
D011314
3
Supertex inc.
www.supertex.com
HV7355
Electrical Characteristics
Sym
I
OUT
R
ON
I
OUT
R
ON
Sym
I
OUT
R
ON
I
OUT
R
ON
Parameter
Output saturation current
Channel resistance
Output saturation current
Channel resistance
Parameter
Output saturation current
Channel resistance
Output saturation current
Channel resistance
(Operating conditions, unless otherwise specified, V
LL
= +3.3V, V
ADD
= V
DD
= +5.0V, V
SS
= -5.0V ,V
PP
= +150V, T
A
= 25°C)
P-Channel MOSFET Output, TX0~7
Min
1.4
-
0.5
-
Min
1.5
-
0.5
-
Typ
1.6
8.0
-
18
Typ
1.7
3.0
-
22
Max
-
-
-
-
Max
-
-
-
-
Units Conditions
A
Ω
A
Ω
MC = 1
100mA
MC = 0
100mA
N-Channel MOSFET Output, TX0~7
Units Conditions
A
Ω
A
Ω
MC = 1
I
SD
= 100mA
MC = 0
100mA
AC Electrical Characteristics
Sym
t
inrf
t
r
t
f
f
OUT
t
EN-ON
t
EN-OFF
t
dr
t
df
t
dm
Δt
DELAY
t
j
Parameter
Input data rise/fall max time
Output rise time
Output fall time
Output frequency range
Initial enable time
Output disable time
Delay time on inputs rise
Delay time on inputs fall
Delay on mode change
Delay time matching
Delay jitter on rise or fall
(Operating
conditions, unless otherwise specified, V
LL
= +3.3V, V
ADD
= V
DD
= +5.0V, V
SS
= -5.0V ,V
PP
= +150V, T
A
= 25°C)
Min
-
-
-
-
-
-
-
-
-
-
-
Typ
-
24
24
-
150
2.0
5.0
5.0
50
± 2.0
15
Max
10
-
-
18
200
5.0
-
-
70
-
-
Units Conditions
ns
ns
ns
MHz
μs
μs
ns
ns
ns
ns
ps
---
330pF//2.5kΩ load
see timing test diagram
100Ω resistor load, V
PP
= +90V
2μF on each CPF pin
to 90% of V
CPF
at 5.0MHz CW
V
PP
= 25V
1.0Ω resistor load, 50% to 50%
see timing test diagram
P to N, channel to channel
---
Serial Data Interface Timing Characteristics
Sym
f
SCK
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
Parameter
Serial clock max. frequency
SDI valid to SCK setup time
SDI valid to SCK hold time
SCK high time
SCK low time
CS pulse width
SCK high to CS high
CS low to SCK high
SDO delay from SCK rise edge
CS high to SCK rise edge
SCK high to LE low
Min
25
0
4.0
9.0
9.0
9.0
7.0
7.0
-
7.0
7.0
Typ
-
2.0
-
-
-
-
-
-
6.5
-
-
(Operating
conditions, unless otherwise specified, V
LL
= +3.3V, V
ADD
= V
DD
= +5.0V, V
SS
= -5.0V ,V
PP
= +150V, T
A
= 25°C)
Max
-
-
-
-
-
-
-
-
-
-
-
Units Conditions
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SDO with 100pF to GND
All from/to 50% rise or fall edges
(See timing diagram)
All from/to 50% rise or fall edges
(See timing diagram)
Doc.# DSFP-HV7355
D011314
4
Supertex inc.
www.supertex.com
HV7355
Output Timing Test Diagram
+3.3V
+5.0V
+5.0 to 150V
VLL
AVDD
VDD
LR
VSS
CPF
VPP
VPF
EN
MC
IN0
PWR
VDD
VPP
CWD
LT
VDD
VPF
VDD
R1
RGND
TX0
Q0
LT
50%
IN
X
t
drx
I
OUT
50%
TX7
+3.3V
Logic
t
dfx
90%
VDD
VPP
VPP
LT
IN7
Q7
Q[7:0]
VDD
VPF
VDD
SET
LE
CS
SCK
SDO
LT
RGND
RGND
TX
X
0A
t
r
10%
t
f
Data Latch
Shift Reg.
Q7
D0
SUB
SDI
VSUB
GND
VSS
-5.0V
Serial Data Interface Timing Diagram
t
1
SCK
t
2
1
t
3
2
t
4
3
7
t
6
8
t
9
SDI
t
5
CS
t
8
SDO
LE
t
10
t
7
Doc.# DSFP-HV7355
D011314
5
Supertex inc.
www.supertex.com
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