The MAX7057 frequency-programmable UHF transmitter
is designed to transmit ASK/FSK data at a wide range
of frequencies from 300MHz to 450MHz. The MAX7057
has internal tuning capacitors at the output of the power
amplifier that are programmable for matching to an
antenna or load. This allows the user to change to a new
frequency and match the antenna at the new frequency
simultaneously. The MAX7057 transmits at a data rate up
to 100kbps nonreturn-to-zero (NRZ) (50kbps Manchester
coded). Typical transmitted power into a 50Ω load is
+9.2dBm with a +2.7V supply. The device operates from
+2.1V to +3.6V and typically draws under 12.5mA of
current in FSK mode (8.5mA in ASK mode) when the
antenna-matching network is designed to operate over
the 315MHz to 433.92MHz frequency range. For narrower
operating frequency ranges, the matching network can be
redesigned to improve efficiency. The standby current is
less than 1µA at room temperature.
The MAX7057 reference frequency from the crystal oscil-
lator is multiplied by a fully integrated fractional-N phase-
locked loop (PLL). The multiplying factor of the PLL is set
by a 16-bit number, with 4 bits for integer and 12 bits for
fraction; the multiplying factor can be anywhere between
19 and 28. The 12-bit fraction in the synthesizer sets a
tuning resolution equal to the reference frequency divided
by 4096; frequency deviation can be set as low as ±2kHz
and as high as ±100kHz. The fractional-N synthesizer
eliminates the problems associated with oscillator-pull-
ing FSK signal generation. The MAX7057 has a serial
peripheral interface (SPI) for selecting all the necessary
settings.
The MAX7057 is available in a 16-pin SO package and
is specified to operate in the -40°C to +125°C automotive
temperature range.
Features
●
Programmable Frequency Operation with Single
Crystal
●
Internal Variable Capacitor for Antenna Tuning with
Single-Matching Network
●
100kbps Data Rate (NRZ)
●
+2.1V to +3.6V Single-Supply Operation
●
< 12.5mA (FSK), < 8.5mA (ASK) DC Current Drain
●
< 1µA Standby Current
●
ASK/FSK Modulation
●
47% Carrier Tuning Range Using One Crystal
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX7057ASE+
-40°C to +125°C
16 SO
+Denotes a lead(Pb)-free/RoHs-compliant package.
Pin Configuration
TOP VIEW
CS
1
SDI 2
SCLK 3
PAGND 4
PAOUT 5
ROUT 6
PAVDD 7
AVDD 8
+
MAX7057
16 DVDD
15 GPO
14 DGND
13 DIN
12 ENABLE
11 AGND
10 XTAL1
9 XTAL2
Applications
●
●
●
●
RF Remote Controls
Garage Door Openers
Home Automation
Wireless Sensors
●
Wireless Game Consoles
●
Wireless Computer
Peripherals
●
Security Systems
Typical Application Circuit and Functional Diagram appear
at end of data sheet.
19-4093; Rev 2; 7/14
MAX7057
300MHz to 450MHz Frequency-Programmable
ASK/FSK Transmitter
Absolute Maximum Ratings
Supply Voltage, PAVDD, AVDD, DVDD to AGND,
DGND, PAGND.................................................-0.3V to +4.0V
All Other Pins............................_GND - 0.3V to _VDD + 0.3V
Continuous Power Dissipation (T
A
= +70°C)
16-Pin SO (derate 8.7mW/°C above +70°C)............695.7mW
Operating Temperature .................................... -40°C to +125°C
Storage Temperature Range ............................ -65°C to +150°C
Lead Temperature (soldering, 10s) ................................. +300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Typical
Application Circuit,
50Ω system impedance, tuned for 315MHz to 433.92MHz operation, V
AVDD
= V
DVDD
= V
PAVDD
= +2.1V
to +3.6V, f
RF
= 300MHz to 450MHz, f
CRYSTAL
= 16MHz, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at V
AVDD
= V
DVDD
= V
PAVDD
= +2.7V, T
A
= +25°C, unless otherwise noted. All min and max values are 100% tested at T
A
= +125°C, and
guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETER
Supply Voltage
SYMBOL
V
DD
CONDITIONS
PAVDD, AVDD, and DVDD connected to
power supply, V
DD
PA off, V
DIN
at 0%
duty cycle (ASK)
V
DIN
at 50% duty
cycle (ASK) (Notes 1, 2, 3)
V
DIN
at 100% duty
cycle (FSK) (Note 1)
f
RF
= 315MHz
f
RF
= 433.92MHz
f
RF
= 315MHz
f
RF
= 433.92MHz
f
RF
= 315MHz
f
RF
= 433.92MHz
T
A
= +25°C (Note 3)
Standby Current
DIGITAL I/O
Input High Threshold
Input Low Threshold
Input Pulldown Sink Current
Input Pullup Source Current
Output-Voltage High
Output-Voltage Low
V
OH
V
OL
I
SINK
= 500µA (GPO)
I
SOURCE
= 500µA (GPO)
V
IH
V
IL
13
9
V
DD
-
0.37
0.36
0.9 x
V
DVDD
0.1 x
V
DVDD
V
V
µA
µA
V
V
I
STDBY
V
ENABLE
< V
IL
T
A
< +85°C (Note 3)
T
A
< +125°C
MIN
2.1
TYP
2.7
3.9
4.5
8.1
8.5
12.2
12.4
0.8
1
6.2
6.4
20.1
µA
MAX
3.6
6.5
7.5
15.1
15.0
23.7
22.4
mA
UNITS
V
DC Electrical Characteristics
Supply Current
I
DD
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Maxim Integrated
│
2
MAX7057
300MHz to 450MHz Frequency-Programmable
ASK/FSK Transmitter
(Typical
Application Circuit,
50Ω system impedance, tuned for 315MHz to 433.92MHz operation, V
AVDD
= V
DVDD
= V
PAVDD
= +2.1V
to +3.6V, f
RF
= 300MHz to 450MHz, f
CRYSTAL
= 16MHz, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at V
AVDD
= V
DVDD
= V
PAVDD
= +2.7V, T
A
= +25°C, unless otherwise noted. All min and max values are 100% tested at T
A
= +125°C, and
guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETER
GENERAL CHARACTERISTICS
Frequency Range
ENABLE transition low-to-high, frequency
settled to within 50kHz of the desired carrier
ENABLE transition low-to-high, frequency
settled to within 5kHz of the desired carrier
ASK mode
Maximum Data Rate
FSK mode
Frequency Switching Time
PHASE-LOCKED LOOP (PLL)
VCO Gain
K
VCO
f
RF
= 315MHz
PLL Phase Noise
f
RF
= 433.92MHz
Loop Bandwidth
Reference Frequency Input Level
Frequency-Divider Range
Frequency Deviation (FSK)
CRYSTAL OSCILLATOR
Crystal Frequency
Frequency Pulling by VDD
Crystal Load Capacitance
POWER AMPLIFIER (PA)
T
A
= +25°C (Note 3)
Output Power (Note 1)
P
OUT
T
A
= +125°C, V
AVDD
= V
DVDD
= V
PAVDD
=
+2.1V
T
A
= -40°C, V
AVDD
= V
DVDD
= V
PAVDD
=
+3.6V (Note 3)
Modulation Depth
Maximum Carrier Harmonics
Reference Spur
With output matching
network
f
RF
= 315MHz
f
RF
= 433.92MHz
3.8
2.4
9.2
5.2
12.6
71
-29
-44
-45
17.0
dB
dBc
dBc
16.4
dBm
(Note 4)
f
XTAL
10.71
16
4
10
23.68
MHz
ppm/V
pF
19
±2
10kHz offset
1MHz offset
10kHz offset
1MHz offset
320
-78
-98
-73
-98
300
500
28
±100
kHz
kHz
mVP-P
dBc/Hz
MHz/V
Manchester encoded
Nonreturn-to-Zero
Manchester encoded
Nonreturn-to-Zero
300
120
µs
260
50
100
50
100
70
µs
kbps
450
MHz
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
AC Electrical Characteristics
Power-On Time
t
ON
Time from end of SPI write to frequency
settled to within 5kHz of desired carrier
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Maxim Integrated
│
3
MAX7057
300MHz to 450MHz Frequency-Programmable
ASK/FSK Transmitter
(Typical
Application Circuit,
50Ω system impedance, tuned for 315MHz to 433.92MHz operation, V
AVDD
= V
DVDD
= V
PAVDD
= +2.1V
to +3.6V, f
RF
= 300MHz to 450MHz, f
CRYSTAL
= 16MHz, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at V
AVDD
= V
DVDD
= V
PAVDD
= +2.7V, T
A
= +25°C, unless otherwise noted. All min and max values are 100% tested at T
A
= +125°C, and
guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETER
Minimum SCLK Low to Falling-
Edge of
CS
Setup Time
Minimum
CS
Low to Rising-Edge
of SCLK Setup Time
Minimum SCLK Low to Rising-
Edge of
CS
Setup Time
Minimum SCLK Low After Rising-
Edge of
CS
Hold Time
Minimum Data Valid to SCLK
Rising-Edge Setup Time
Minimum Data Valid to SCLK
Rising-Edge Hold Time
Minimum SCLK High Pulse Width
Minimum SCLK Low Pulse Width
Minimum
CS
High Pulse Width
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SERIAL INTERFACE (SPI) TIMING CHARACTERISTICS (Figure 1)
t
SC
t
CSS
t
HCS
t
HS
t
DS
t
DH
t
CH
t
CL
t
CSH
10
5
20
5
10
5
40
40
40
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC Electrical Characteristics (continued)
Maximum Transition Time from
CL = 10pF load capacitance from GPO to
t
CSG
Falling-Edge of
CS
to Valid GPO
DGND
Maximum Transition Time from
CL = 10pF load capacitance from GPO to
Falling-Edge of SCLK to Valid
t
CG
DGND
GPO
Note 1:
Supply current and output power are greatly dependent on board layout and PAOUT match.
Note 2:
50% duty cycle at 10kHz ASK data (Manchester coded).
Note 3:
Guaranteed by design and characterization, not production tested.