Standard Products
UT1750AR RadHard RISC Microprocessor
Data Sheet
September 2001
FEATURES
q
Operates in either RISC (Reduced Instruction Set
Computer) mode or MIL-STD-1750A mode
q
Supports MIL-STD-1750A 32-bit floating-point
operations and 48-bit extended-precision floating-point
operations on chip
q
Built-in 9600 baud UART
q
Supports defined MIL-STD-1750A Console Mode of Operation
q
Full 64K-word address space. Expandable to 1M words with
optional MMU (operand port)
q
Register-oriented architecture has 21 user-accessible registers
q
Registers may be in 16-bit word or 32-bit double-word
configurations
RISC
MEMORY
CONTROL
BUS
ARBITRA-
TION
PROCES-
SOR
STATUS
q
Built-in multiprocessor bus arbitration and Direct Memory Access
support (DMA)
q
TTL-compatible I/O
q
Stable 1.5-micron CMOS technology
q
Full military operating range, -55°C to +125°C, in accordance
with MIL-PRF-38535 for Class Q and V
q
Typical radiation performance
-
-
-
-
Total dose: 1.0E6 rads(Si)
SEL Immune . 100 MeV-cm
2
/mg
LET
TH
(0.25) = 60 MeV-cm
2
/mg
Saturated Cross Section (cm
2
) per bit, 1.2E-7
- 2.3E-11 errors/bit-day, Adams to 90% geosynchronous heavy ion
q
Standard Military Drawing 5962-01502
16
UART
TIMCLK
TEST
UARTOUT
UARTIN
OE
WE
BRQ
BGNT
BUSY
BGACK
NUI1
NUI2
M1750
STATE1
MME
NUO3
CONSOLE
OSCOUT
OSCIN SYSCLK
OSCILLATOR
/CLOCK
SHIFT REG
PROCESSOR
CONTROL
LOGIC
IR
RISC MAP
32
GENERAL
PURPOSE
REGISTERS
BIT REG
TBR
RBR
TR
16
16
16
16
16
16
16
32
32
32
TB
IM
FR
PI
ST
SW
TEMP DEST
TEMP SRC
I/O
MUX
RISC DATA
RISC
ADDRESS
or O/P DISC
RISC
ADDRESS
SYSFL
BTERR
MPAR
MPROT
PFAIL
IOLINT1
IOLINT0
INT0-5
MRST
4
16
32
32
8
16
4
IC/ICs
RISC
ADD
MUX
I
N
T
E
R
R
U
P
T
S
32
ACC
32
16
PIPELINE
PR
A MUX
B MUX
BUS
CONTROL
16
32-BIT ALU
1750 SP
1750 PC
16
32
16
PS0-3
AS0-3
OPERAND
DATA
OP/IN
DTACK
M/IO
R /W R
AS
DS
OPERAND
ADDRESS
ADDR
MUX
6
Figure 1. UT1750AR Functional Block Diagram
RD0 - RD15
RA19/CS
RA18/OD1
RA17/OD2
RA16/OD3
RA15
RA14
RA13
RA12
RA11
RA10
RA9
RA8
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
RISC DATA PORT
BUS
ARBITRATION
BRQ
BGNT
BUSY
BGACK
OP/IN
DTACK
BUS
CONTROL
M/IO
R/WR
AS
DS
UT1750AR
RISC
ADDRESS
BUS
CLOCK
SYSCLK
AS0
AS1
AS2
AS3
MODE
NUI1
NUI2
M1750
MME
CONSOLE
STATE1
OSCIN
OSCOUT
UARTIN
UARTOUT
TIMCLK
TEST
PROCESSOR
STATUS
PS0
PS1
PS2
PS3
NUO3
OSCILLATOR
OE
WE
MEMORY
UART
SYSFLT
BTERR
MPAR
MPROT
INT5
INT4
INT3
INT2
INT1
INT0
PFAIL
IOLINT0
IOLINT1
MRST
A0
A1
A2
A3
INTERRUPTS/
EXCEPTIONS
OPERAND
ADDRESS
BUS
A4
A5
A6
A7
A8
A9
A10
A11
OPERAND
DATA BUS
A12
A13
A14
A15
D0 - D15
Figure 2. UT1750AR Pin Function Diagram
2
GENERAL DESCRIPTION
The UT1750AR (figures 1 and 2) is a high performance
monolithic CMOS 16-bit RISC microprocessor that supports
the complete MIL-STD-1750A Instruction Set Architecture
(ISA). Underlying the MIL-STD-1750A support is a high-
performance RISC that provides MIL-STD-1750A emulation
capability. Developed to provide effective real-time avionics
processing, the high performance of the native RISC machine
is available to the MIL-STD-1750A systems designer through
the MIL-STD-1750A Built-In-Function (BIF) opcode.
The UT1750AR is the first member of a family of high-
performance MIL-STD-1750 processors and support
peripherals from UTMC.
PRODUCT DESCRIPTION
The UTMC UT1750AR operates in its native RISC language
mode or MIL-STD-1750A ISA mode. As a MIL-STD-1750A
microprocessor, the UT1750AR requires 8K x 16 of ROM to
map the MIL-STD-1750A instruction set into the native RISC
machine language instructions. Each MIL-STD-1750A opcode
has a unique RISC code macro in the external ROM. The
UT1750AR executes the corresponding resident RISC code
macro to perform the MIL-STD-1750A instruction
requirements. When in this mode and operating with a 12 MHz
clock, the UT1750AR can throughput 600 KIPS using the DAIS
mix (800 KIPS @ 16 MHz).
The native RISC language mode is available to the user when
the UT1750AR is operating as MIL-STD-1750A processor
through MIL- STD-1750A’s Built-In Function (BIF) opcode.
When operating as a RISC processor, the UT1750AR executes
most RISC instructions in two clock cycles. Thus, a 12 MHz
operating clock frequency provides up to 6 MIPS of RISC
throughput (8 MIPS @16 MHz). This high execution rate, along
with its efficient architecture, make the RISC mode especially
effective in applications requiring real-time processing.
The architecture of the UT1750AR is based around 20 user-
accessible, 16-bit general purpose registers providing the
programmer with extensive register support. The UT1750AR’s
flexibility is enhanced by its ability to concatenate the 16-bit
registers into ten 32-bit registers. In addition, all registers are
available for use as either the source or the destination for any
register operation.
The UT1750AR fully supports multiprocessor, DMA, and
complex bus arbitration for managing the system bus and
preventing bus contention. Bus control passes among bus
masters operating on the same bus. The bus masters can be
several UT1750ARs or any other device requiring Direct
Memory Access, such as a MIL-STD-1553B interface.
The UT1750AR supports 16 levels of vectored interrupts. Ten
of these are external interrupts, eight of which are user-
definable. All 16 interrupt levels are prioritized and serviced in
order of priority.
When used as a MIL-STD-1750A microprocessor, the
UT1750AR’s instruction set supports 16-bit fixed-point single-
precision and 32-bit fixed-point double-precision data formats.
Also, the UT1750AR can emulate 32-bit floating-point and 48-
bit floating-point extended-precision data in two’s complement
representation.
In its native RISC mode, the UT1750AR’s three basic
instruction formats support 16-bit and 32-bit instructions. The
formats are Register-to-Register, Register-to-Literal, and
Register-to-Long-Immediate instructions.
Figure 3 shows the UT1750AR’s general system architecture,
its emulation ROM, instruction and data memory, and the
system interface. The emulation ROM is isolated from the
system; only the UT1750AR microprocessor accesses it.
RISC DATA
16
EMULATION
ROM
(8K X 16)
RISC ADDRESS
16
UT1750AR
OPERAND DATA
16
CONTROL
OPERAND ADDRESS
16
MIL-STD-1750A
MEMORY
INSTRUCTIONS
DATA
Figure 3. UT1750AR MIL-STD-1750A General System Architecture
3
FUNCTIONAL PINOUT
Legend for TYPE and ACTIVE fields:
TO
TI
TUI
TDI
TTO
=
=
=
=
=
TTL output
TTL input
TTL input (pull-up)
TTL input (pull-down)
Three-state TTL output
TTB
CO
OSC
AH
AL
=
=
=
=
=
Three-state TTL bidirectional
CMOS output
Oscillator input to a Pierce Oscillator inverter
Active High
Active Low
OSCILLATOR AND CLOCK SIGNALS
PIN NAME
OSCIN
OSCOUT
PIN NUMBER
FLTPK
PGA
50
P14
51
P15
TYPE
OSC
CO
ACTIVE
--
--
DESCRIPTION
Oscillator Input. A 50% duty cycle crystal-drive input for
driving the UT1750AR.
Oscillator Output. A 50% duty cycle, single-phase clock
output at the same frequency as the OSCIN input.
System Output. The buffered equivalent of the OSCOUT
signal.
SYSCLK
52
M14
TO
--
PROCESSOR STATUS
PIN NAME
NUI1
PIN NUMBER
FLTPK
PGA
129
H2
TYPE
TI
ACTIVE
--
DESCRIPTION
Not used input 1. Internal UTMC use only. Tie either high
or low.
NUI2
44
P12
TUI
--
Not used input 2. Internal UTMC use only. Tie low.
NUO3
126
G3
TTO
--
Not used output 3. Internal UTMC use only. NUO3 enter
high impedance state when the UT1750AR is in the test
mode (TEST=0)
M1750
45
N11
TDI
AH
Mode Select RISC/1750. A high on M1750 places the
UT1750AR into the MIL-STD-1750A emulation mode.
A low on M1750 places the UT1750AR into the RISC
mode. It is tied to an internal pull-down resistor.
Processor State. This signal indicates the internal state of
the UT1750AR. A low on STATE1 indicates the
UT1750AR is executing a new RISC instruction. A high
on STATE1 indicates the UT1750AR is fetching a RISC
instruction. STATE1 enters a high-impedance state when
the UT1750AR is in the test mode (TEST=0).
STATE1
54
N15
TTO
--
4
OPERAND DATA BUS ARBITRATION
PIN NAME
BRQ
PIN NUMBER
FLTPK
PGA
118
D2
TYPE
TTO
ACTIVE
AL
DESCRIPTION
Bus Request. The UT1750AR asserts this signal to indicate
it is requesting control of the Operand data bus (D0 - D15).
BRQ enters a high-impedance state when the UT1750AR is
in the test mode (TEST = 0).
Bus Grant. When asserted, this signal indicates the
UT1750AR may take control of the Operand data bus. It is
tied to an internal pull-up resistor.
Bus Busy. A bus master asserts this input to inform the
UT1750AR that another bus master is using the Operand
data bus. It is tied to an internal pull-up resistor.
Bus Grant Acknowledge Output. The UT1750AR asserts
this signal to indicate it is the current bus master. When low,
BGACK inhibits other devices from becoming the bus
master. When the UT1750AR relinquishes control of the
bus, BGACK enters a high-impedance state.
BGNT
119
E3
TUI
AL
BUSY
120
C1
TUI
AL
BGACK
117
B1
TTO
AL
OPERAND DATA BUS CONTROL
PIN NAME
OP/IN
PIN NUMBER
FLTPK
PGA
113
A2
TYPE
TTO
ACTIVE
--
DESCRIPTION
Operand/Instruction. This indicates whether the
UT1750AR’s current bus cycle is for Data (high) or
Instruction (low) acquisition. OP/IN remains in a high
state whenever a bus cycle (Memory or I/O) is not an
instruction fetch.
Data Transfer Acknowledge. This signal tells the
UT1750AR that a data transfer has been acknowledged
and the UT1750AR can complete the bus cycle. To assure
the UT1750AR operates with no wait states,DTACK can
be tied low. DTACK is tied to an internal pull-up resistor.
DTACK
121
E2
TUI
AL
M/IO
112
B3
TTO
--
Memory or I/O. Indicates whether the current bus cycle
is for memory (high) or I/O (low). It remains in the high-
impedance state during bus cycles when the UT1750AR
does not control the Operand busses.
Read/Write. Indicates the direction of data flow with
respect to the UT1750AR. R/WR high means the
UT1750AR is attempting to read data from an external
device, and R/WR low means the UT1750AR is
attempting to write data to an external device. R/WR
remains in a high-impedance state when the UT1750AR
does not control the Operand busses.
Continued on page 6.
5
R/WR
114
C4
TTO
--
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
