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access
RS8234
Plus with
ATM ServiceSAR
xBR Traffic Management
datasheet
PROVIDING
HIGH
SPEED
MULTIMEDIA
CONNECTIONS
September 1998
Preliminary Information
This document contains information on a product under development. The parametric information contains target
parameters that are subject to change.
RS8234
ATM ServiceSAR Plus with xBR Traffic Management
The RS8234 Service Segmentation and Reassembly Controller integrates ATM
terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with
service specific functions in a single package. The
ServiceSAR
Controller generates
and terminates ATM traffic as well as automatically scheduling cells for transmission.
The RS8234 is targeted at 155 Mbps throughput systems where the number of VCCs
is relatively large, or the performance of the overall system is critical. Examples of
such networking equipment include Routers, Ethernet switches, ATM Edge switches,
or Frame Relay switches.
Distinguishing Features
Service-Specific Performance
Accelerators
• LECID filtering and echo
suppression
• Dual leaky bucket based on CLP
(frame relay)
• Frame relay DE interworking
• Internal SNMP MIB counters
• IP over ATM; supports both
CLP0+1 and ABR shaping
Flexible Architectures
•
•
Multi-peer host
Direct switch attachment via
reverse UTOPIA
• ATM terminal
– Host control
– Local bus control
• Optional local processor
New Features
•
•
•
•
3.3 V, 388 BGA lowers power and
eases PCB assembly
AAL3/4 CPCS generation and
checking
PCI 2.1, including support for
serial EEPROM
Enhancements to xBR Traffic
Manager
– fewer ABR templates
– improved CBR tunneling
Reduced memory size for VCC
lookup tables
Increased addressing flexibility
Additional byte lane swappers for
increased system flexibility
Service-Specific Performance Accelerators
The RS8234 incorporates numerous service-specific features designed to accelerate
and enhance system performance. As examples, the RS8234 implements Echo
Suppression of LAN traffic via LECID filtering, and supports Frame Relay DE to CLP
interworking.
Advanced xBR Traffic Management
The xBR Traffic Manager in the RS8234 supports multiple ATM service categories.
This includes CBR, VBR (both single and dual leaky bucket), UBR, GFR (Guaranteed
Frame Rate) and ABR. The RS8234 manages each VCC independently. It dynamically
schedules segmentation traffic to comply with up to 16+CBR user-configured
scheduling priorities for the various traffic classes. Scheduling is controlled by a
Schedule Table configured by the user and based on a user-specified time reference.
ABR channels are managed in hardware according to user programmable ABR
templates. These templates tune the performance of the RS8234’s ABR algorithms to
a specific system’s or network’s requirements.
-continued-
•
•
•
-continued-
Functional Block Diagram
Local Bus
Local Memory
Interface
Segmentation
Coprocessor
PCI
Multi-client
PCI Bus
DMA
Reassembly
Coprocessor
CBR, VBR, ABR,
UBR, GFR
Traffic Manager
Master/ Co-
Slave proc’r
Timer
Counters
Control/
Status
UTOPIA
Master/Slave
Cell
FIFO
Rx/Tx
RS8250
PHY
Device
RS8234
Patent Pending
Preliminary N8234DSC
Ordering Information
Model Number
RS8234EBGB
Manufacturing
Part Number
28234-12
Product
Revision
C
Package
388-pin BGA
Operating Temperature
–40°C to 85°C
Copyright © 1998 Rockwell Semiconductor Systems, Inc. All rights reserved.
Print date: September 1998
Rockwell Semiconductor Systems, Inc. reserves the right to make changes to its products or specifications to improve
performance, reliability, or manufacturability. Information furnished is believed to be accurate and reliable. However, no
responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its
use. No license is granted by its implication or otherwise under any patent or intellectual property rights of Rockwell
Semiconductor Systems, Inc.
Rockwell Semiconductor Systems, Inc. products are not designed or intended for use in life support appliances, devices, or
systems where malfunction of a Rockwell Semiconductor Systems, Inc. product can reasonably be expected to result in personal
injury or death. Rockwell Semiconductor Systems, Inc. customers using or selling Rockwell Semiconductor Systems, Inc.
products for use in such applications do so at their own risk and agree to fully indemnify Rockwell Semiconductor Systems, Inc.
for any damages resulting from such improper use or sale.
Bt is a registered trademark of Rockwell Semiconductor Systems, Inc.
Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered
trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders.
Specifications are subject to change without notice.
PRINTED IN THE UNITED STATES OF AMERICA
Preliminary N8234DSC
-continued from front-
Multi-Queue Segmentation Processing
The RS8234’s segmentation coprocessor generates ATM
cells for up to 64 kB VCCs at a line rate of up to 200 Mbps
for simplex connections. The segmentation coprocessor
formats cells on each channel according to segmentation
VCC Tables, utilizing up to 32 independent transmit
queues and reporting segmentation status on a parallel
set of up to 32 segmentation status queues. The
segmentation coprocessor fetches client data from the
host, formats ATM cells while generating and appending
protocol overhead, and forwards these to the UTOPIA
port. The segmentation coprocessor operates as a slave
to the xBR Traffic Manager which schedules VCCs for
transmission.
High Performance Host Architecture with
Buffer Isolation
The RS8234 host interface architecture maximizes
performance and system flexibility. The device’s control
and status queues enable host/SAR communication via
write operations alone. This lowers latency and PCI bus
occupancy. Flexibility is achieved by supporting a
scalable peer-to-peer architecture. Multiple host clients
may be addressed by the SAR as separate physical or
logical PCI peers. Segmentation and reassembly data
buffers on the host system are identified by buffer
descriptors in SAR shared (or host) memory which
contain pointers to buffers. The use of buffer descriptors
in this way allows for isolation of data buffers from the
mechanisms that handle buffer allocation and linking.
This provides a layer of indirection in buffer assignment
and management that maximizes system architecture
flexibility.
Multi-Queue Reassembly Processing
The RS8234’s reassembly coprocessor stores the
payload data from the cell stream received by the UTOPIA
port into host data buffers. Using a dynamic lookup
method which supports NNI or UNI addressing, the
reassembly coprocessor processes up to 64 kB VCCs
simultaneously. The host supplies free buffers on up to
32 independent free buffer queues, and the reassembly
coprocessor performs all CPCS protocol checks and
reports the results of these checks as well as other status
data on one of 32 independent reassembly status queues.
Designer Toolkit
Rockwell provides an evaluation environment for the
RS8234 which provides a working reference design, an
example software driver, and facilities for generating and
terminating all service categories of ATM traffic. This
system accelerates ATM system development by
providing a rapid prototyping environment.
Preliminary N8234DSC
-continued Distinguishing Features-
xBR Traffic Management
•
TM4.0 Service Classes
– CBR
– VBR (single, dual and CLP-
based leaky buckets)
– Real time VBR
– ABR
– UBR
– GFC (controlled & uncon-
trolled flows)
– Guaranteed Frame Rate
(GFR) (guaranteed MCR on
UBR VCCs)
16 Levels of priorities (16 + CBR)
Dynamic per-VCC scheduling
Multiple programmable ABR
templates (supplied by Rockwell
or user)
Scheduler driven by local system
clock for low jitter CBR
Internal RM OAM cell feedback
path
Virtual FIFO rate matching
(Source Rate Matching)
Per-VCC MCR and ICR.
Tunneling
– VP tunnels (VCI interleaving
on PDU boundaries)
– CBR tunnels (cells interleaved
as UBR, VBR or ABR with an
aggregate CBR limit)
Multi-Queue Reassembly Processing
•
•
•
•
32 reassembly queues
64 kB VCCs maximum *
AAL5 & AAL3/4 CPCS checking
AAL0
– PTI termination
– Cell count termination
Early Packet Discard, based on:
– Receive buffer underflow
– Receive status overflow
– CLP with priority threshold
– AAL5 max PDU length
– Rx FIFO full
– Frame relay DE with priority
threshold
– LECID filtering and echo sup-
pression
– Per-VCC firewalls
Dynamic channel lookup (NNI or
UNI addressing)
– Supports full address space
– Deterministic
– Flexible VCI count per VPI
– Optimized for signalling
address assignment
Message and streaming status
modes
Raw cell mode (52 octet)
200 Mbps half duplex
155 Mbps full duplex (w/ 2-cell
PDUs)
Distributed host or SAR shared
memory reassembly
8 Programmable reassembly
hardware time-outs (per-VCC
assignable)
Global max PDU length for AAL5
Per-VCC buffer firewall (memory
usage limit)
Simultaneous reassembly and
segmentation
Idle cell filtering
32 kB duplex VCCs
•
•
•
•
•
Automatically detects presence of
Tx data or Rx free buffers
Virtual FIFOs (PCI bursts treated
as a single address)
Hardware indication of BOM
Allows isolation of system
resources
Status queue interrupt delay
•
Designer Toolkit
•
•
•
Evaluation hardware and
software
Reference schematics
Hardware Programming
Interface - RS823xHPI reference
Source code (C)
•
•
•
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•
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•
•
Generous Implementation of OAM-PM
Protocols
• Detection of all F4/F5 OAM flows
• Internal PM monitoring and
generation for up to 128 VCCs
• Optional global OAM Rx/Tx
queues
• In-Line OAM insertion &
generation
Standards-Based I/O
• 33 MHz PCI 2.1
• Serial EEPROM to store PCI
configuration information
• PHY interfaces
– UTOPIA master (Level 1)
– UTOPIA slave (Level 1)
• Flexible SAR shared memory
architecture
• Optional local control interface
• Boundary scan for board-level
testing
• Source loopback, for diagnostics
• Glueless connection to
Rockwell’s ATM physical layer
device, the RS8250
Standards Compliance
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•
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UNI/NNI 3.1
TM 4.0
Bellcore GR-1248
ATM Forum B-ICI V2.0
I.363
I.610 /GR-1248
AToM MIB (RFC1695)
ILMI MIB
ANSI T1.635
GFC per I.361
SNMP
I
2
C protocol
PCI Revision 2.1
IEEE 1149.1-1990
IEEE 1149.1 Supplement B, 1994
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Multi-Queue Segmentation Processing
•
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32 transmit queues with optional
priority levels
64 kB VCCs maximum *
AAL5 & AAL3/4 CPCS generation
AAL0 Null CPCS (optional use of
PTI for PDU demarcation)
ATM cell header generation
Raw cell mode (52 octet)
200 Mbps half duplex
155 Mbps full duplex (w/ 2-cell
PDUs)
Variable length transmit FIFO -
CDV - host latency matching (1 to
9 cells)
Symmetric Tx and Rx
architecture
– buffer descriptors
– queues
User defined field circulates back
to the host (32 bits)
Distributed host or SAR shared
memory segmentation
Simultaneous segmentation and
reassembly
Per-PDU control of CLP/PTI
(UBR)
Per-PDU control of AAL5 UU field
Message & streaming status
modes
Virtual Tx FIFO (PCI host)
•
•
•
•
•
High Performance Host Architecture
with Buffer Isolation
• Write-only control and status
• Read multiple command for data
transfer
• Up to 32 host clients control and
status queues
• Physical or logical clients
– Enables peer-to-peer archi-
tecture
• Descriptor-based buffer chaining
• Scatter/gather DMA
• Endian neutral (allows data word
and control word byte swapping,
for both big and little endian
systems)
• Non-word (byte) aligned host
buffer addresses
•
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Preliminary N8234DSC
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