Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
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Features
•
PLL with quartz stabilized VCXO
•
Loss of signals alarm
•
Return to nominal clock upon LOS
•
Input data rates from 8 kb/s to 65 Mb/s
•
Tri-state output
•
User defined PLL loop response
•
NRZ data compatible
•
Single +5.0V power supply
Description
The device is composed of a phase-lock loop with an
integrated VCXO for use in clock recovery, data re-
timing, frequency translation and clock smoothing
applications in telecom and datacom systems.
Crystal Frequencies Supported: 12.000~50.000 MHz.
Block Diagram
CLKIN
DATAIN
HIZ
Phase Detector &
Loss Of Signal
Circuit
RCLK
RDATA
LOS
PHO
VC
LOSIN
CLK1
VCXO
Divider
CLK2
OPN
Op
Amp
OPOUT
OPP
Ordering Information
PT7V4050
Device Type
16-pin clock recoverymodule
PackageLeads
T: Thru-Hole
G: Surface Mount
CLK2 Divider
A: Divide by 2 E: Divide by 32
B: Divide by 4 F: Divide by 64
C: Divide by 8 G: Divide by 128
D: Divide by 16 H: Divide by 256
K: Disable
T
B
C
G
A
49.408 / 12.352
CLK2 Frequency
CLK1 Frequency
A: 5.0V supply voltage
B: 3.3V supply voltage
C:
±
20ppm
F:
±
32ppm
G:
±
50ppm
H:
±
100ppm
Temperature Range
C: 0
°
C to 70
°
C
T: -40
°
C to 85
°
C
12.000
16.128
18.432
22.579
28.000
34.368
44.736
Frequencies using at CLK1 (MHz)
12.288
12.624
13.00
16.384
16.777
16.896
18.936
20.000
20.480
24.576
24.704
25.000
30.720
32.000
32.768
38.880
40.000
41.2416
47.457
49.152
49.408
19.440
35.328
16.000
17.920
22.1184
27.000
33.330
41.943
50.000
40.960
Note:
CLK1 up to 40.960MHz for both 5V and
3.3V for temperature -40oC to 85 oC; CLK1 up to
50MHz for both 5V and 3.3V for temperature 0oC to 70oC.
PT0125(02/06)
1
Ver:2
Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
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Pin Configuration
VC
1
16
15
14
13
12
11
10
9
V
CC
CLK1
HIZ
CLK2
RDATA
RCLK
LOS
CLKIN
OPN 2
OPOUT 3
OPP 4
LOSIN 5
PHO 6
DATAIN 7
GND 8
Pin Description
P in No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P in Na m e
VC
Typ e
I
Descr ip t ion
Control voltage input to internal voltage controlled crystal oscillator (VCXO).
Negative input terminal to internal operational amplifier.
Output terminal of internal operational amplifier.
Positive input terminal to internal operational amplifier.
TTL input. When LOSIN is set to HIGH, VC disabled, and when set to LOW, VC to
VCXO are enabled. (Internal pull-down resistor)
Output signal of phase detector.
TTL input. Input data stream to phase detector.
Ground.
TTL input. Input clock to phase detector.
Signal loss indication for DATAIN, high active.
Output recovered clock.
Output recovered data stream.
Output clock with divided function.
TTL input. When HIZ is set to LOW, the device is in standby state and the outputs are
set to high impedance. (Internal pull-up resistor)
Output clock of internal VCXO frequency.
5V power supply
OPN
OPOUT
OPP
LOSIN
PHO
DATAIN
GND
CLKIN
LOS
RCLK
RDATA
CLK2
HIZ
CLK1
V
CC
I
O
I
I
O
I
G
I
O
O
O
O
I
O
P
Notes:
1. LOSIN input sets to HIGH, VC is disabled and the VCXO returns to its nominal center frequency. When sets to LOW, VC to
VCXO is enabled.
2. LOS output sets to HIGH, if no transitions are detected at DATAIN after 256 clock cycles. LOS output sets to LOW as soon
as a transition occurs at DATAIN.
3. HIZ input sets LOW, output pins CLK1, CLK2, RCLK, and RDATA buffers are set to high-impedance state. When set to logic
high or no connection, the device functions and output pins CLK1, CLK2, RCLK, and RDATA etc. are active.
PT0125(02/06)
2
Ver:2
Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested)
Note:
Stresses greater than those listed under MAXI-
Storage Temperature ........................................................ -55
o
C to +125
o
C
MUM RATINGS may cause permanent damage to
Power Supply Voltage ............................................................. -0.5 to +7V the device. This is a stress rating only and func-
Input High Voltage .................................................................... +7V Max. tional operation of the device at these or any other
Input Low Voltage .................................................................... -0.5V Min. conditions above those indicated in the operational
sections of this specification is not implied. Expo-
sure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
DC Electrical Characteristics
Symbol
V
CC
I
LEAK
V
TIH
V
TIL
V
OH1
V
OL1
V
OH2
V
OL2
I
PULLUP
I
PULLDOWN
I
CC
T
A
Parameters
Supply Voltage
Input Leakage Current
TTL Input High Voltage
TTL Input Low Voltage
Output High Voltage for CLK1
& 2, RCLK&RDATA
Output Low Voltage for CLK1
& 2, RCLK&RDATA
Output High Voltage for LOS
Output Low Voltage for LOS
Input Pull up Current for HIZ
Input Pull down Current for
LOSIN
Maximum Supply Current
Ambient Temperature
Ioh = -8mA
Iol = 8mA
Ioh = -3mA
Iol = 3mA
-160
50
Full Active
-40
60
85
2.4
0.4
2.4
0.4
Conditions
0~V
DD
Min
4.5
-10
2
0.8
Max
5.5
10
Units
V
µA
V
V
V
V
V
V
µA
µA
mA
o
C
PT0125(02/06)
3
Ver:2
Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
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AC Electrical Characteristics
Parameter
Input NRZ Data Rates
Input RZ Data and Clock Rates
Nominal Output Frequency
Clock Output 1
Clock Output 2
Transition Times:
Rise Time (0.5V to 2.5V)
Fall Time (2.5V to 0.5V)
Symmetry or Duty cycle (VS = 1.4V)
CLK1
CLK2
RCLK
Control Voltage Bandwidth (-3 dB,VC =
0.5V
CC
)
Sensitivity @ VC = V
CC
/2
Nominal Output Frequency on Loss of Signal:
Clock Output 1 & 2
Phase Detector Gain
Symbol
DATAIN
DATAIN
CLK1
CLK2
t
R
t
F
SYM 1
SYM 2
RCLK
BW
∆F/∆VC
CLK1
CLK2
KD
-75
-75
0.53
x Data
Density
Min
0.008
0.008
12.00
CLK1 /256
0.5
0.5
40
45
40
20
100
75
75
Typical
Max
65.536
32.768
65.536
CLK1 /2
5
5
60
55
60
Unit
M b/s
M b/s
MHz
MHz
ns
ns
%
%
%
kHz
ppm/V
ppm from fo 1
ppm from fo 2
V/rad
PT0125(02/06)
4
Ver:2
Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
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Packaging Information
16-pin Surface Mount (G)
20.32
10.16
2.54
4.15
1.73
10.16
1.2
20.32
PT0125(02/06)
10.16
6.7
5
Ver:2
FPGA/CPLD
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