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UCC3588
5 BIT PROGRAMMABLE OUTPUT BiCMOS
POWER SUPPLY CONTROLLER
SLUS311A – JULY 1999 – REVISED AUGUST 2000
D
5-Bit Digital-to-Analog Converter (DAC)
D
D
D
D
D
D
D
D
D
D
supports Intel Pentium II
Microprocessor VID Codes
Compatible with 5-V or 12-V Systems
1% Output Voltage Accuracy Ensured
Drives 2 N-Channel MOSFETs
Programmable Frequency to 800 kHz
Power Good OV / UV / OVP Voltage Monitor
Undervoltage Lockout and Softstart
Functions
Short Circuit Protection
Low Impedance MOSFET Drivers
Chip Disable
D, J, N AND PW PACKAGES
(TOP VIEW)
VSENSE
ISNS
SS/ENBL
D0
D1
D2
D3
D4
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RT
VCC
DRVLO
DRVHI
GND
PWRGOOD
VFB
COMP
AVAILABLE OPTIONS
PACKAGED DEVICES
TJ
0°C TO 70°C
D, 16-PIN
UCC3588D
J, 16-PIN
UCC3588J
N, 16-PIN
UCC3588N
PW, 16-PIN
UCC3588PW
description
The UCC3588 synchronous step-down (Buck) regulator provides accurate high efficiency power conversion.
Using few external components, the UCC1588 converts 5V to an adjustable output ranging from 3.5 VDC to
2.1 VDC in 100-mV steps and 2.05 VDC to 1.3 VDC in 50-mV steps with 1% dc system accuracy. A high level
of integration and novel design allow this 16-pin controller to provide a complete control solution for today’s
demanding microcontroller power requirements. Typical applications include on board or VRM based power
conversion for Intel Pentium II microprocessors, as well as other processors from a variety of manufacturers.
High efficiency is obtained through the use of synchronous rectification.
The softstart function provides a controlled ramp up of the system output voltage. Overcurrent circuitry detects
a hard (or soft) short on the system output voltage and invokes a timed softstart/shutdown cycle to reduce the
PWM controller on time to 5%.
The oscillator frequency is externally programmed with RT and operates over a range of 50 kHz to 800 kHz.
The gate drivers are low impedance totem pole output stages capable of driving large external MOSFETs. Cross
conduction is eliminated by fixed delay times between turn off and turn on of the external high side and
synchronous MOSFETs. The chip includes undervoltage lockout circuitry which assures the correct logic states
at the outputs during power up and power down.
This device is available in 16-pin surface mount, plastic and ceramic DIP, and TSSOP packages. The UCC3588
is specified for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2000, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
SLUS311A – JULY 1999 – REVISED AUGUST 2000
UCC3588
5 BIT PROGRAMMABLE OUTPUT BiCMOS
POWER SUPPLY CONTROLLER
application diagram
12 V IN
5 V IN
+
C16
10
µF
R1
10 k
UCC3588
15
+
C1
D0
D1
D2
D3
D4
+
C2
+
C3
+
C4 C1–C4
500
µF
11
4
5
6
7
8
3
PWRGOODDRVLO 14
D0
D1
D2
D3
D4
SS/ENBL
RT
16
GND
12
R7
15 k
R2
47 k
C13
1 nF
RTN
ISNS
VSENSE
VFB
COMP
2
1
10
9
+
C8
+
C9
+
C10
+
C11
+
C12
+
C14
150
µF
R5
3
Ω
VCC
DRVHI 13
R4
3
Ω
Q1
IRL3103
L1
1.6
µH
Q2
IRL3103
C15
150
µF
R6
0.003Ω
C8–C12 1500
µF
VOUT
C6
R3
200 k 220 pF
C7 22 pF
D1
D2
C5
33 nF
R8
20 k
RTN
UDG-98158
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Gate drive current, 50% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
Input voltage, V
SENSE
, V
FB
, SS, COMMAND, COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V
Input voltage, D0, D1, D2, D3, D4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input current, RT, COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and
considerations of packages. All voltages are referenced to GND.
thermal data
Plastic DIP package,
thermal resistance junction to leads,
Θjc
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45°C/W
thermal resistance junction to ambient,
Θja
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
Ceramic DIP package,
thermal resistance junction to leads,
Θjc
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28°C/W
thermal resistance junction to ambient,
Θja
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
Standard surface mount package,
thermal resistance junction to leads,
Θjc
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35°C/W
thermal resistance junction to ambient,
Θja
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
NOTE The above numbers for
Θ
ja and
Θ
jc are maximums for the limiting thermal resistance of the package in a standard mounting configuration.
The
Θ
ja numbers are meant to be guidelines for the thermal performance of the device and PC board system. All of the above numbers
assume no ambient airflow, see the packaging section of Unitrode Product Data Handbook for more details.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
UCC3588
5 BIT PROGRAMMABLE OUTPUT BiCMOS
POWER SUPPLY CONTROLLER
SLUS311A – JULY 1999 – REVISED AUGUST 2000
electrical characteristics,
T
A
= 0°C to 70°C. T
A
= T
J
. V
CC
= 12 V, RT = 49 k, (unless otherwise stated)
PARAMETER
Supply Current Section
Supply current, on
UVLO Section
VCC UVLO turnon threshold
UVLO threshold hysteresis
Voltage Error Amplifier Section
Input bias current
Open loop gain
Output voltage high
Output voltage low
Output source current
Output sink current
Oscillator/PWM Section
Initial accuracy
Ramp amplitude (p–p)
Ramp valley voltage
PWM max duty cycle
PWM min duty cycle
PWM delay to outputs (high to low)
PWM delay to outputs (low to high)
Transient Window Comparator Section
Detection range high (duty cycle = 0)
Detection range low (duty cycle = 1)
Propagation delay (VSENSE to outputs)
Soft Start/ Shutdown Section
SS charge current (normal start-up)
SS charge current
(short circuit fault condition)
SS discharge current
(during timeout sequence)
Shutdown threshold
Restart threshold
Soft start complete threshold (normal start–
up)
Measured on SS
Measured on SS
Measured on SS
Measured on SS
Measured on SS
Measured on SS
–6
–60
1
4.1
0.4
3.5
–100
2.5
4.2
0.5
3.7
–12
–120
5
4.3
0.6
3.9
mA
mA
mA
V
V
V
% Over VCOMMAND,
% Under VCOMMAND,
See Note 1
See Note 1
3
–3
150
200
%
%
nS
COMP = 3 V
COMP = 0. 3 V
COMP = 1.5 V
COMP = 1.5 V
See Note 5
See Note 5
See Note 5
See Note 5
0°C < TA < 70°C
250
270
1.85
0.65
100
0
150
150
290
kHz
V
V
%
%
ns
ns
VCM = 2.0 V
See Note 5
ICOMP = –500 mA
ICOMP = 500 mA
VVFB = 2 V,
VVFB = 3 V,
VCOMMAND = VCOMP = 2.5 V
VCOMMAND = VCOMP = 2.5 V
3.5
–400
5
–0.025
77
3.6
0.2
–500
10
0.5
–0.050
mA
dB
V
V
mA
mA
10.05
350
10.50
450
10.85
550
V
mV
VCC = 12 V,
VRT = 2 V
4.5
5.5
mA
TEST CONDITIONS
MIN
TYP
MAX
UNITS
NOTES: 1. This percentage is measured with respect to the ideal command voltage programmed by the VID (D0,....,D4) pins and applies to all
DAC codes from 1.3 V to 3.5 V.
2. Reference and error amplifier offset trimmed while the voltage amplifier is set in unity gain mode.
3. Deadtime delay is measured from the 50% point of DRVHI falling to the 50% point of DRVLO rising, and vice-verse.
4. This time is dependent on the value of CSS.
5. Ensured by design. Not 100% production tested.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SLUS311A – JULY 1999 – REVISED AUGUST 2000
UCC3588
5 BIT PROGRAMMABLE OUTPUT BiCMOS
POWER SUPPLY CONTROLLER
electrical characteristics,
T
A
= 0°C to 70°C. T
A
= T
J
. V
CC
= 12 V, RT = 49 k, (unless otherwise stated)
PARAMETER
TEST CONDITIONS
10.8 V < VCC < 13.2 V,
0°C < TA < 70°C,
measured on COMP,
See Note 2
MIN
TYP
MAX
UNITS
DAC / Reference Section
COMMAND voltage accuracy
D0 to D4 voltage high
D0 to D4 voltage threshold
D0 to D4 voltage input bias current
Overvoltage Comparator Section
Trip point
Hysteresis
Undervoltage Comparator Section
Trip point
Hysteresis
PWRGOOD Signal Section
Output impedance
Overvoltage Protection Section
Trip point
Hysteresis
VSENSE input bias current
Gate Drivers (DRVHI, DRVLO) Section
Output high voltage
Output low voltage
Driver non-overlap time
(DRVHI– to DRVLO+)
Driver non-overlap time
(DRVLO– to DRVHI+)
Driver rise time
Driver fall time
Current Limit Section
Start of quick charge to shutdown threshold
Current limit threshold voltage
ISNS input bias current
VISNS = VSENSE + 75 mV, CSS = 10 nF,
See Note 4,
See Note 5
VTHRESHOLD = VISNS – VVSENSE
40
–8
50
54
–12
70
–16
ms
mV
mA
IGATE = 100 mA, VCC = 12 V
IGATE =–100 mA, VCC = 12 V
See Note 3
See Note 3
3 nF capacitive load
3 nF capacitive load
10.8
11.5
0.5
90
50
120
80
80
80
0.8
150
120
100
100
V
V
ns
ns
ns
ns
OV, OVP, UV combined
–8
% Over VCOMMAND,
See Note 1
15
17.5
20
–12
20
35
–16
%
mV
mA
VCC = 12 V,
IPWRGOOD = 1 mA
470
W
% Under VCOMMAND,
See Note 1
–8.0
10
20
–12.0
35
%
mV
% Over VCOMMAND,
See Note 1
8
10
20
12
35
%
mV
V(D4,...,D0) < 0.5 V
–1.0
5.5
2.5
–80
6
3.0
–100
1.0
6.5
3.5
%
V
V
mA
NOTES: 6. This percentage is measured with respect to the ideal command voltage programmed by the VID (D0,....,D4) pins and applies to all
DAC codes from 1.3 V to 3.5 V.
7. Reference and error amplifier offset trimmed while the voltage amplifier is set in unity gain mode.
8. Deadtime delay is measured from the 50% point of DRVHI falling to the 50% point of DRVLO rising, and vice-verse.
9. This time is dependent on the value of CSS.
10. Ensured by design. Not 100% production tested.
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
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