Approval sheet
Capacitor Arrays Series
1. INTRODUCTION
WTC middle and high voltage series MLCC is designed by a special internal electrode pattern, which can reduce
voltage concentrations by distributing voltage gradients throughout the entire capacitor. This special design also affords
increased capacitance values in a given case size and voltage rating.
WTC capacitor arrays are developed to offer designers the opportunity to lower placement costs increase assembly
line output through lower component count per board.
2. FEATURES
a.
b.
c.
High density mounting due to mounting space
saving.
Mounting cost saving.
Increased throughput.
3. APPLICATIONS
a.
b.
c.
For use as a bypass for digital and analog signal
line noise
Computer motherboards and peripherals.
The other common electronic circuits.
4. HOW TO ORDER
Y
Series
4C
Cap. Nr.
3
B
103
K
Tolerance
J=±5%
K=±10%
M=±20%
Z=-20/+80%
500
Rated voltage
C
Termination
T
Packaging
T=7”
reeled
Termination pitch Dielectric Capacitance
N=NP0
(C0G)
B=X7R
F=Y5V
Two significant
digits followed
by no. of zeros.
And R is in
place of
decimal point.
eg.:
103=10x10
3
=10,000pF
=10nF
Y=Capacitor 4C=4xCap 3=0.03”
pitch
array
2=0.02”
pitch
Two significant
C=Cu/Ni/Sn
digits followed
by no. of zeros.
And R is in
place of decimal
point.
eg.:
100=10
VDC
160=16
VDC
250=25
VDC
500=50
VDC
Page 2 of 8
ASC_ Cap_Arrays_005M_AS
Oct. 2012
Approval sheet
Capacitor Arrays Series
5. EXTERNAL DIMENSIONS
L
W
S
T
BW
P
Fig. 1 The outline of MLCC
Size
Inch (mm)
0508 (1220)
0612 (1632)
L (mm)
2.00±0.15
3.20±0.15
W (mm)
1.25±0.15
1.60±0.15
T (mm)/Symbol
0.85±0.10
0.80±0.10
T
B
S (mm)
0.20±0.10
0.30±0.20
BW (mm)
0.25±0.10
0.40±0.15
P (mm)
0.50±0.10
0.80±0.15
Reflow soldering process only.
6. GENERAL ELECTRICAL DATA
Dielectric
Size
Capacitance*
Capacitance tolerance**
Rated voltage (WVDC)
Q/Tan
δ*
Insulation resistance at Ur
Operating temperature
Capacitance characteristic
Termination
±30ppm
4x0402
10pF to 270pF
50V
NP0
4x0603
10pF to 470pF
25, 50V
4x0402
1000pF to 100nF
10V, 16V, 25V, 50V
X7R
4x0603
180pF to 100nF
16V, 25V, 50V
Y5V
4x0603
10nF to 100nF
Z (-20/+80%)
16V, 50V
Ur=50V,
≤5%
Ur=16V,
≤7%
J (±5%), K (±10%)
K (±10%), M (±20%)
Ur=50V,
≤2.5%
Ur=25V&16V,
≤3.5%
Ur=10V,
≤5.0%
≥10G
-55 to +125°
C
±15%
Ni/Sn (lead-free termination)
Cap<30pF: Q≥400+20C
Cap≥30pF: Q≥1000
≥10G
or RxC≥500 xF whichever is less
-25 to +85°
C
+30/-80%
* Measured at 30~70% related humidity.
NP0: Apply 1.0±0.2Vrms, 1.0MHz±10% at the conditions of 25° ambient temperature.
C
X7R: Apply 1.0±0.2Vrms, 1.0kHz±10%, at the conditions of 25° ambient temperature.
C
Y5V: Apply 1.0±0.2Vrms, 1.0kHz±10%, at the conditions of 20° ambient temperature.
C
** Preconditioning for Class II MLCC: Perform a heat treatment at 150±10° for 1 hour, then leave in a mbient condition for 24±2 hours
C
before measurement.
Page 3 of 8
ASC_ Cap_Arrays_005M_AS
Oct. 2012
Approval sheet
Capacitor Arrays Series
9. RELIABILITY TEST CONDITIONS AND REQUIREMENTS
No.
1.
2.
3.
Item
Visual and
Mechanical
Capacitance
Q/ D.F.
(Dissipation
Factor)
Class I: (NP0)
1.0±0.2Vrms, 1MHz±10%
Class II: (X7R, Y5V)
1.0±0.2Vrms, 1kHz±10%
---
Test Condition
* No remarkable defect.
Requirements
* Dimensions to conform to individual specification sheet.
* Shall not exceed the limits given in the detailed spec.
NP0: Cap≥30pF, Q≥1000; Cap<30pF, Q≥400+20C
X7R: Ur=50V,
≤2.5%;
Ur=25V&16V,
≤3.5%;
Ur=10V,
≤5.0%
Y5V: Ur=50V,
≤5%;
Ur=16V,
≤7%
4.
Dielectric
Strength
* To apply 250% rated voltage.
* Duration: 1 to 5 sec.
* Charge and discharge current less than 50mA.
* No evidence of damage or flash over during test.
5.
6.
Insulation
Resistance
Temperature
Coefficient
To apply rated voltage for max. 120 sec.
≥10G
or RxC≥500 -F whichever is smaller.
With no electrical load.
T.C.
NP0
X7R
Y5V
Operating Temp
-55~125° at 25°C
C
-55~125° at 25°C
C
-25~85° at 20°
C
C
T.C.
NP0
X7R
Y5V
Capacitance Change
Within ±30ppm/°
C
Within ±15%
Within +30%/-80%
7.
Adhesive
Strength of
Termination
* Pressurizing force：
5N (≤0603) and 10N (>0603)
* Test time: 10±1 sec.
* Vibration frequency: 10~55 Hz/min.
* Total amplitude: 1.5mm
* Test time: 6 hrs. (Two hrs each in three mutually
perpendicular directions.)
* Measurement to be made after keeping at room temp. for
24±2 hrs.
* No remarkable damage or removal of the terminations.
8.
Vibration
Resistance
* No remarkable damage.
* Cap change and Q/D.F.: To meet initial spec.
9.
10.
Solderability
* Solder temperature: 235±5°
C
* Dipping time: 2±0.5 sec.
95% min. coverage of all metalized area.
Bending Test
* The middle part of substrate shall be pressurized by means
* No remarkable damage.
of the pressurizing rod at a rate of about 1 mm per second until * Cap change：
the deflection becomes 1 mm and then the pressure shall be
maintained for 5±1 sec.
* Measurement to be made after keeping at room temp. for
24±2 hrs.
NP0: within ±5.0% or ±0.5pF whichever is larger.
X7R: within ±12.5%
Y5V: within ±30%
(This capacitance change means the change of capacitance under
specified flexure of substrate from the capacitance measured before
the test.)
11.
Resistance to
* Solder temperature: 260±5°
C
* No remarkable damage.
* Cap change:
NP0: within ±2.5% or ±0.25pF whichever is larger.
X7R: within ±7.5%
Y5V: within ±20%
* Q/D.F., I.R. and dielectric strength: To meet initial requirements.
* 25% max. leaching on each edge.
Soldering Heat
* Dipping time: 10±1 sec
* Preheating: 120 to 150° for 1 minute before imme rse the
C
capacitor in a eutectic solder.
* Before initial measurement (Class II only): Perform
150+0/-10° for 1 hr and then set for 24±2 hrs at r oom temp.
C
* Measurement to be made after keeping at room temp. for
24±2 hrs.
Page 5 of 8
ASC_ Cap_Arrays_005M_AS
Oct. 2012
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