GMM7658287CNTG-5/6
8,388,608WORDS x 64 BIT
CMOS EDO DYNAMIC RAM MODULE
Description
The GMM7658287CNTG is an 8M x 64 bits
Dynamic RAM MODULE which is assembled 8
pieces of 4M x 16bit DRAMs in 50pin TSOP
package, one 2k EEPROM for SPD in 8-pin
TSSOP package mounted on a 144 pin printed
circuit board with decoupling capacitors.
The GMM7658287CNTG is optimized for
application to the systems which are required high
density and large capacity such as main memory of
the computers and an image memory systems, and
to the others which are requested compact size.
The GMM7658287CNTG provides common data
inputs and Extended Data Outputs.
Features
* 144 pins Dual In-Line Package
- GMM7658287CNTG : Gold plating
* Extended Data Out(EDO)Mode Capability
* Single Power Supply
* Fast Access Time & Cycle Time
(Unit: ns)
Speed
GMM7658287CNTG-5
GMM7658287CNTG-6
t
RAC
t
CAC
t
RC
50
60
13
15
84
104
t
HPC
20
25
GMM7658287CNTG(Both
Side)
* Low Power
Active : 2,044/ 2,188 mW (MAX)
Standby : 8.64 mW (CMOS level : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 4096 Refresh Cycles/128ms
* Self Refresh Operation
* Battery Back-up Operation
Pin Configuration
(Top View)
144
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
Pin Symbol
2
* This Data Sheet is subject to change without notice.
1
143
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Vss
Vss
DQ0
DQ32
DQ1
DQ33
DQ2
DQ34
DQ3
DQ35
Vcc
Vcc
DQ4
DQ36
DQ5
DQ37
DQ6
DQ38
DQ7
DQ39
Vss
Vss
/CE0
/CE4
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
/CE1
/CE5
Vcc
Vcc
A0
A3
A1
A4
A2
A5
Vss
Vss
DQ8
DQ40
DQ9
DQ41
DQ10
DQ42
DQ11
DQ43
Vcc
Vcc
DQ12
DQ44
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
Vss
Vss
RSVD
RSVD
RSVD
RSVD
RFU
RFU
Vcc
Vcc
RFU
RFU
/WE
RFU
/RE0
RFU
/RE1
RFU
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
/OE
RFU
Vss
Vss
RSVD
RSVD
RSVD
RSVD
Vcc
Vcc
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
Vss
Vss
DQ20
DQ52
DQ21
DQ53
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ22
DQ54
DQ23
DQ55
Vcc
Vcc
A6
A7
A8
A11
Vss
Vss
A9
A12*
A10
A13*
Vcc
Vcc
/CE2
/CE6
/CE3
/CE7
Vss
Vss
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
Vcc
Vcc
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
Vss
Vss
SDA
SCL
Vcc
Vcc
Note : Pins Marked
*
are not used in this module.
1
GMM7658287CNTG-5/6
Block Diagram
/RE0
/RE1
/WE
/OE
/RAS /WE /OE
/CE0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
/CE1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
/LCAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/UCAS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/RAS /WE /OE
/LCAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
D4
I/O7
/UCAS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/CE4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
/CE5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
/RAS /WE /OE
/LCAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/UCAS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/RAS /WE /OE
/LCAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/UCAS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
D0
D2
D6
/CE2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
/CE3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
/RAS /WE /OE
/LCAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
D1
/UCAS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/RAS /WE /OE
/LCAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
D5
/UCAS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/RAS /WE /OE
/CE6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
/CE7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
/LCAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/UCAS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
D3
/RAS /WE /OE
/LCAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
D7
/UCAS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
Serial PD
A0~A11
D0~D7
SCL
V
CC
V
SS
0.22§
Þ
Capacitor
under each DRAM
To all DRAMS
A0
D8
A1
A2
SDA
2
GMM7658287CNTG-5/6
Pin Description
Pin
A0-A11
DQ0-DQ63
RE0,RE1
CE0-CE7
WE
SDA
SCL
Function
Address Inputs
Data Input/Output
Row Address Strobe
Column Address Strobe
Read/Write Enable
Serial Address / Data I/O
Serial Clock
Pin
OE
V
CC
V
SS
NC
Function
Output Enable
Power (+3.3V)
Ground
No Connection
RSVD
SA0-SA2
RFU
Reserved Use
Address in EEPROM
Reserved for Future use
Serial Presence Detect Information
. SPD Interface Protocol : IIC
. Current sink capability of SDA driver < 3 mA
. Maximum Clock Frequency : 100 KHz
Byte
0
1
2
3
4
5
6
Function described
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type(FPM, EDO..) form appendix A
# Row Address on this assembly
# Column Address on this assembly
# Module Banks on this assembly
Data Width of this assembly
Module Data Width continuation
Voltage interface standard of this assembly
RAS # Access time of this assembly
CAS # Access time of this assembly
DIMM Configuration type(Non-Parity,Parity,ECC)
Refresh Rate/Type
DRAM Width, Primary DRAM
Error checking DRAM data width
Reserved for future offerings
Superset memory type(may be used in future)
Function supported
128 bytes
256 bytes
EDO
Hex Value
80h
08h
02h
0Ch
0Ah
02h
40h
00h
01h
32h
0Dh
00h
83h
10h
00h
00h
00h
12
10
2
64bits
N/A
LVTTL
t
RAC
= 50 ns
t
CAC
= 13 ns
Non-Parity
4096/128ms
x16
0
7
8
9
10
11
12
13
14
15-31
32
* Above data are based on the SPD specification of JEDEC standard.
3
GMM7658287CNTG-5/6
Byte
33-62
63
64
65-71
72
73
Manufacturing location
Manufacturer`s part number
=== Allowed characters include 0-9, A-Z and space ===
Korea
GMM7658287CNTG-50
Function described
Superset memory specific features(may be used in future)
Checksum for bytes 0-62
Manufacturers JEDEC ID code per JEP-106E
Function supported
Hex Value
00h
B5h
LGS
E0h
00h
52h
47h(G)
4Dh(M)
4Dh(M)
37h(7)
36h(6)
35h(5)
38h(8)
32h(2)
38h(8)
37h(7)
43h(C)
4Eh(N)
54h(T)
47h(G)
2Dh(-)
35h(5)
20h
20h
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91-92
93
94
95-98
99-125
126-127
128-255
Revision Code
Date Code
Rev0
WW
YY
00h
00h
61h(97)
00h
00h
00h
00h
Assembly serial number
Manufacturer specific data
Reserved
Open User Free-Form area $ not defined
Binary incremental
N/A
* Above data are based on the SPD specification of JEDEC standard.
4
GMM7658287CNTG-5/6
Absolute Maximum Ratings*
Symbol
T
STG
V
T
V
CC
I
OUT
P
D
Parameter
Storage Temperature (Plastic)
Voltage on any Pin Relative to V
SS
Voltage on any Pin Relative to V
SS
Short Circuit Output Current
Power Dissipation
Rating
-55 to 125
-0.5 to Vcc +0.5
-0.5 to 4.6
50
8
Unit
C
V
V
mA
W
*
Note: 1. Stress greater than above Absolute Maximum Ratings may cause permanent damage to the device.
Recommended DC Operating Conditions
(T
A
= 0 ~ 70C)
Symbol
V
CC
V
IH
V
IL
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Min
3.0
2.0
-0.3
Typ
3.3
-
-
Max
3.6
Vcc+0.3
0.8
Unit
V
V
V
Note
1
1
1
*
Note: 1. All voltages referenced to V
SS
.
5