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SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048
×
9, 4096
×
9, 8192
×
9, 16384
×
9
ASYNCHRONOUS FIRST IN, FIRST OUT MEMORIES
SCAS226A − FEBRUARY 1993 − REVISED SEPTEMBER 1995
D
Reads and Writes Can Be Asynchronous
D
or Coincident
Organization:
− SN74ACT7203L − 2048
×
9
− SN74ACT7204L − 4096
×
9
− SN74ACT7205L − 8192
×
9
− SN74ACT7206L − 16383
×
9
Fast Data Access Times of 15 ns
Read and Write Frequencies up to 40 MHz
Bit-Width and Word-Depth Expansion
Fully Compatible With the IDT7203 / 7204
Retransmit Capability
Empty, Full, and Half-Full Flags
TTL-Compatible Inputs
Available in 28-Pin Plastic DIP (NP), Plastic
Small-Outline (DV), and 32-Pin Plastic
J-Leaded Chip-Carrier (RJ) Packages
DV OR NP PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
D
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
D4
D5
D6
D7
FL /RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
RJ PACKAGE
(TOP VIEW)
These devices are constructed with dual-port
SRAM and have internal write and read address
counters to provide data throughput on a first-in,
first-out (FIFO) basis. Write and read operations
are independent and can be asynchronous or
coincident. Empty and full status flags prevent
underflow and overflow of memory, and
depth-expansion logic allows combining the
storage cells of two or more devices into one
FIFO. Word-width expansion is also possible.
Data is loaded into memory by the write-enable
(W) input and unloaded by the read-enable (R)
input. Read and write cycle times of 25 ns
(40 MHz) are possible with data access times of
15 ns.
D2
D1
D0
XI
FF
Q0
Q1
NC
Q2
D3
D8
W
NC
V
CC
D4
D5
4
5
6
7
8
9
10
11
12
3 2 1 32 31 30
29
28
27
26
25
24
23
22
13
21
14 15 16 17 18 19 20
description
D6
D7
NC
FL /RT
RS
EF
XO/HF
Q7
Q6
Q3
Q8
NC − No internal connection
These devices are particularly suited for providing a data channel between two buses operating at
asynchronous rates. Applications include use as rate buffers from analog-to-digital converters in
data-acquisition systems, temporary storage elements between buses and magnetic or optical memories, and
queues for communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus
a parity bit or packet-framing information. The read pointer can be reset independently of the write pointer for
retransmitting previously read data when a device is not used in depth expansion.
The SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, and SN74ACT7206L are characterized for operation
from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1995, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
GND
NC
R
Q4
Q5
1
SCAS226A − FEBRUARY 1993 − REVISED SEPTEMBER 1995
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048
×
9, 4096
×
9, 8192
×
9, 16384
×
9
ASYNCHRONOUS FIRST IN, FIRST OUT MEMORIES
SN74ACT7203L logic symbol
†
FIFO 2048
×
9
Φ
SN74ACT7203L
22
RS
W
1
2,4 CT = 0 (RST)
6 (WR PNTR)
6 C1
G2
XI
FL /RT
7
23
(EXPAND)
(1ST LOAD)
2,4 (REXMIT)
15
R
5 (RD PNTR)
5EN3
G4
(CT = WR PNTR − RD PNTR)
D0
D1
D2
D3
D4
D5
D6
D7
D8
6
5
4
3
27
26
25
24
2
1D
3
9
10
11
12
16
17
18
19
13
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
(EXPAND)
CT > 1024
20
XO/HF
2(CT = 2047) G6
4(CT = 2047) G6
(CT = 2048) G6
(CT = 0) G5
21
EF
8
FF
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DV and NP packages.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048
×
9, 4096
×
9, 8192
×
9, 16384
×
9
ASYNCHRONOUS FIRST IN, FIRST OUT MEMORIES
SCAS226A − FEBRUARY 1993 − REVISED SEPTEMBER 1995
SN74ACT7204L logic symbol
†
FIFO 4096
×
9
Φ
SN74ACT7204L
22
RS
W
1
2,4 CT = 0 (RST)
6 (WR PNTR)
6 C1
G2
XI
FL /RT
7
23
(EXPAND)
(1ST LOAD)
2,4 (REXMIT)
15
R
5 (RD PNTR)
5EN3
G4
(CT = WR PNTR − RD PNTR)
D0
D1
D2
D3
D4
D5
D6
D7
D8
6
5
4
3
27
26
25
24
2
1D
3
9
10
11
12
16
17
18
19
13
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
(EXPAND)
CT > 2048
20
XO/HF
2(CT = 4095) G6
4(CT = 4095) G6
(CT = 4096) G6
(CT = 0) G5
21
EF
8
FF
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DV and NP packages.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
3
SCAS226A − FEBRUARY 1993 − REVISED SEPTEMBER 1995
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048
×
9, 4096
×
9, 8192
×
9, 16384
×
9
ASYNCHRONOUS FIRST IN, FIRST OUT MEMORIES
SN74ACT7205L logic symbol
†
FIFO 8192
×
9
Φ
SN74ACT7205L
22
RS
W
1
2,4 CT = 0 (RST)
6 (WR PNTR)
6 C1
G2
XI
FL /RT
7
23
(EXPAND)
(1ST LOAD)
2,4 (REXMIT)
15
R
5 (RD PNTR)
5EN3
G4
(CT = WR PNTR − RD PNTR)
D0
D1
D2
D3
D4
D5
D6
D7
D8
6
5
4
3
27
26
25
24
2
1D
3
9
10
11
12
16
17
18
19
13
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
(EXPAND)
CT > 4096
20
XO/HF
2(CT = 8191) G6
4(CT = 8191) G6
(CT = 8192) G6
(CT = 0) G5
21
EF
8
FF
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DV and NP packages.
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
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