AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AVED2M321JSMW/KSMW
FAST PAGE MODE 2MX32 DRAM SIMM, 1K REFRESH, 5V
DESCRIPTION
AVED Memory Products AVED2M321JSMW/KSMW is a
2M bit x 32 Dynamic RAM high density memory module.
The AVED Memory Products AVED2M321JSMW/KSMW
consists of four CMOS 1Mx16bit DRAMs in 20-pin SOJ
packages mounted on a 72-pin glass-epoxy substrate.
A 0.22uf decoupling capacitor is mounted on the printed
circuit board for each DRAM. The AVED Memory Products
AVED2M321JSMW/KSMW is a Single In-Line Memory
Module with edge connections and is intended for mounting
into 72 pin edge connector sockets.
APPLICATION
Main Memory unit for computer, Microcomputer memory,
Refresh memory for CRT.
FEATURES
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
Symbol
Vss
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
Vcc
NC
Pin
37
38
39
40
41
42
43
44
45
46
47
Symbol
NC
NC
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
NC
W
NC
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
•
Performance Ranges
Speed
-60
-70
tRAC
60ns
70ns
tCAC
15ns
20ns
tRC
110ns
130ns
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
A0
A1
A2
A3
A4
A5
A6
NC
DQ4
DQ20
DQ5
DQ21
DQ6
DQ22
DQ7
DQ23
A7
NC
Vcc
A8
A9
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
•
Part Identification
- AVED2M321JSMW-XX
1024 cycles/16ms Ref, SOJ, Tin Contact Plating
- AVED2M321KSMW-XX
1024 cycles/16ms Ref, SOJ, Gold Contact Plating
- (XX= -60, -70)
•
Fast Page Mode Operation
•
•
•
•
refresh capability
RAS
-only and Hidden refresh capability
TTL compatible inputs and outputs
Single +5V
±
10% power supply
CAS
-before-
RAS
DQ11
DQ27
DQ12
DQ28
Vcc
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
PD1
PD2
PIN NAMES
A0 - A9
DQ0 - DQ31
W
RAS0
-
RAS3
,
CAS0
-
CAS3
PD1 - PD4
Address Inputs
Data In/Out
Read/Write Input
Row Address Strobe
Column Address Strobe
PRESENCE DETECT PINS (Optional)
Pin
PD1
PD2
PD3
PD4
60NS
NC
NC
NC
NC
70NS
NC
NC
Vss
NC
Vcc
Vss
NC
Presence Detect
Power (+5V)
Ground
No Connection
Revision: 1.0
Revision Date: 12/00
Document number: 30225
RAS3
page number: 1 of 6
69
PD3
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AVED2M321JSMW/KSMW
FAST PAGE MODE 2MX32 DRAM SIMM, 1K REFRESH, 5V
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Storage Temperature
Power Dissipation
Short Circuit Output Current
*
Symbol
V
IN
, VOUT
Vcc
Tstg
Pd
IOS
Rating
-1 to +7.0
-1 to +7.0
-55 to +150
9.6
50
Unit
V
V
ºC
W
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, Ta = 0 to 70ºC)
Item
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
Vcc
Vss
VIH
VIL
Min
4.5
0
2.4
-1.0
Typ
5.0
0
-
-
Max
5.5
0
Vcc+1
0.8
Unit
V
V
V
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Symbol
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
I1(L)
I0(L)
VOH
VOL
ICC1:
ICC2:
ICC3:
ICC4:
ICC5:
ICC6:
I1(L):
I0(L):
VOH:
VOL:
*
Speed
-60
-70
-
-60
-70
-60
-70
-
-60
-70
-
-
-
-
AVED2M321SSM4/LSM4
Min
Max
-
-
-
-
-
-
-
-
-
-
-160
-20
2.4
-
616
536
32
616
536
456
376
16
616
536
160
20
-
0.4
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
Operating Current * (
RAS
,
CAS
,
Address cycling @tRC=min.)
Standby Current (
RAS
=
CAS
=
W
= VIH)
RAS
Only Refresh Current * (
CAS
= VIH,
RAS
cycling @tRC = min.)
Fast Page Mode Current * (
RAS
=VIL,
CAS
, Address cycling : tPC=min.)
Standby Current (
RAS
=
CAS
=
W
=Vcc-0.2V)
CAS
-Before-
RAS
Refresh Current * (
RAS
and
CAS
cycling @ tRC = min.)
Input Leakage Current (Any input 0
£
VIN
£
Vcc+0.5V, all other pins not under test = 0 V.)
Output Leakage Current (Data out is disabled, 0V
£
Vout
£
Vcc)
Output High Voltage Level (IOH = -5mA)
Output Low Voltage Level (IOL = 4.2mA)
NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is
specified as an average current. In ICC1 and ICC3, address can be changed maximum two times while
RAS
=VIL. In ICC4, address can be
changed maximum once within one page mode cycle.
Revision: 1.0
Revision Date: 12/00
Document number: 30225
page number: 2 of 6
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AVED2M321JSMW/KSMW
FAST PAGE MODE 2MX32 DRAM SIMM, 1K REFRESH, 5V
CAPACITANCE
(Ta = 25
ºC,
f=1MHz)
Item
Input capacitance [A0-A9]
Input capacitance [
W
]
Input capacitance
[
RAS0
-
RAS3
]
Input capacitance [
CAS0
-
CAS3
]
Input/Output capacitance [DQ0-31]
Symbol
CIN1
CIN2
CIN3
CIN4
CDQ1
Min
-
-
-
-
-
Max
128
140
42
42
29
Unit
pF
pF
pF
pF
pF
AC CHARACTERISTICS
(0ºC
£
Ta
£
70ºC, Vcc=5.0V
±
10%. See notes 1,2.)
-60
STANDARD OPERATION
Random read or write cycle time
Access time from
RAS
Access time from
CAS
Access time from column address
CAS
-70
Max
Min
130
60
15
30
70
20
35
0
15
50
10K
0
3
50
70
20
70
10K
45
30
20
20
15
5
0
10
0
15
55
35
0
0
0
15
55
15
20
20
0
10K
50
35
10K
20
50
Symbol
tRC
tRAC
tCAC
tAA
tCLZ
tOFF
tT
tRP
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tAR
tRAL
tRCS
tRCH
tRRH
tWCH
tWCR
tWP
tRWL
tCWL
tDS
Min
110
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
3,4
3,4,5
3,11
3
7
2
to output in Low-Z
0
0
3
40
60
15
60
15
20
15
5
0
10
0
15
50
30
0
0
0
10
45
10
15
15
0
Output buffer turn-off delay
Transition time (rise and fall)
RAS
precharge time
RAS
pulse width
RAS
hold time
CAS
hold time
CAS
pulse width
RAS
to
CAS
delay time
RAS
to column address delay time
CAS
to
RAS
precharge time
4
11
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address hold time referenced to
RAS
Column address to
RAS
lead time
Read command set-up time
Read command hold time referenced to
CAS
Read command hold time referenced to
RAS
Write command hold time
Write command hold time referenced to
RAS
Write command pulse width
Write command to
RAS
lead time
Write command to
CAS
lead time
Data set-up time
6
9
9
6
10
Revision: 1.0
Revision Date: 12/00
Document number: 30225
page number: 3 of 6
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AVED2M321JSMW/KSMW
FAST PAGE MODE 2MX32 DRAM SIMM, 1K REFRESH, 5V
AC CHARACTERISITICS
(continued)
-60
STANDARD OPERATION
Data hold time
Data hold time referenced to
RAS
Refresh period
Write command set-up time
CAS
set-up time (
CAS
- before -
RAS
refresh)
CAS
hold time (
CAS
- before -
RAS
refresh)
RAS
precharge to
CAS
hold time
-70
Max
Min
15
55
16
16
0
10
15
5
35
40
45
10
100K
70
10
10
25
100K
Symbol
tDH
tDHR
tREF
tWCS
tCSR
tCHR
tRPC
tCPA
tPC
tCP
tRASP
tWRP
tWRH
tCPT
Min
15
50
0
10
10
5
40
10
60
10
10
20
Max
Unit
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
10
6
8
Access time from
CAS
precharge
Fast Page mode cycle time
CAS
precharge time (Fast Page cycle)
RAS
pulse width (Fast Page cycle)
W
to
RAS
precharge time
(
C
-B-
R
refresh)
W
to
RAS
hold time
(
C
-B-
R
refresh)
CAS
precharge
3
(
C
-B-
R
refresh)
Revision: 1.0
Revision Date: 12/00
Document number: 30225
page number: 4 of 6
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AVED2M321JSMW/KSMW
FAST PAGE MODE 2MX32 DRAM SIMM, 1K REFRESH, 5V
NOTES
1.
An initial pause of 200ms is required after power-up
followed by any 8
RAS
-only or
CAS
-before-
RAS
refresh cycles before proper device operation is
achieved.
8.
2.
VIH (min) and VIL (max) are reference levels for
measuring timing of input signals. Transition times are
measured between VIH (min) and VIL (max) and are
assumed to be 5ns for all inputs.
3.
Measured with a load equivalent to 2TTL loads and
100pF.
Operation within the tRCD (max) limit insures that tRAC
(max) can be met. tRCD (max) is specified as a
reference point only. If tRCD is greater than the
specified tRCD (max) limit, then access time is
controlled exclusively by tCAC.
5.
6.
Assumes that tRCD
³
tRCD (max).
tAR, tWCR, tDHR are referenced to tRAD (max).
10. These parameters are referenced to the
leading edge in early write cycles.
CAS
7.
This parameter defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
tWCS is non-restrictive operating parameter.
It is included in the data sheet as electrical
characteristic only. If tWCS
³
tWCS (min) the cycle
is an early write cycle and the data out pin will
remain high impedance for the duration of the
cycle.
9.
Either tRCH or tRRH must be satisfied for a read
cycle.
4.
11. Operation within the tRAD (max) limit insures that
tRAC (max) can be met. tRAD (max) is specified as
a reference point only. If tRAD is greater than the
specified tRAD (max) limit, then access time is
controlled by tAA.
Revision: 1.0
Revision Date: 12/00
Document number: 30225
page number: 5 of 6
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