LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
IDT72V81
IDT72V82
IDT72V83
IDT72V84
IDT72V85
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The IDT72V81 is equivalent to two IDT72V01 - 512 x 9 FIFOs
The IDT72V82 is equivalent to two IDT72V02 - 1,024 x 9 FIFOs
The IDT72V83 is equivalent to two IDT72V03 - 2,048 x 9 FIFOs
The IDT72V84 is equivalent to two IDT72V04 - 4,096 x 9 FIFOs
The IDT72V85 is equivalent to two IDT72V05 - 8,192 x 9 FIFOs
Low power consumption
— Active: 330 mW (max.)
— Power-down: 18 mW (max.)
Ultra high speed—15 ns access time
Asynchronous and simultaneous read and write
Offers optimal combination of data capacity, small foot print
and functional flexibility
Ideal for bidirectional, width expansion, depth expansion, bus-
matching, and data sorting applications
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CMOS™ technology
Space-saving TSSOP package
Industrial temperature range (–40°C to +85°C) is available
°
°
Green parts available, see ordering information
DESCRIPTION:
The IDT72V81/72V82/72V83/72V84/72V85 are dual-FIFO memories that
load and empty data on a first-in/first-out basis. These devices are functional and
compatible to two IDT72V01/72V02/72V03/72V04/72V05 FIFOs in a single
package with all associated control, data, and flag lines assigned to separate
pins. The devices use Full and Empty flags to prevent data overflow and
underflow and expansion logic to allow for unlimited expansion capability in both
word size and depth.
The reads and writes are internally sequential through the use of ring
pointers, with no address information required to load and unload data. Data
is toggled in and out of the devices through the use of the Write (W) and Read
(R) pins.
The devices utilize a 9-bit wide data array to allow for control and parity
bits at the user’s option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability that allows for reset
of the read pointer to its initial position when
RT
is pulsed low to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
These FIFOs are fabricated using high-speed CMOS technology. They are
designed for those applications requiring asynchronous and simultaneous
read/writes in multiprocessing and rate buffer applications.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(DA
0
-DA
8
)
WA
WRITE
CONTROL
WRITE
POINTER
THREE-
STATE
BUFFERS
RSA
WB
WRITE
CONTROL
WRITE
POINTER
DATA INPUTS
(DB
0
-DB
8
)
RSB
RAM
ARRAY A
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
READ
POINTER
RAM
ARRAY A
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
READ
POINTER
THREE-
STATE
BUFFERS
RA
READ
CONTROL
FLAG
LOGIC
EXPANSION
LOGIC
RESET
LOGIC
READ
CONTROL
FLAG
LOGIC
EXPANSION
LOGIC
RESET
LOGIC
XIA
XOA/HFA
FFA
EFA
DATA
OUTPUTS
(QA
0
-QA
8
)
FLA/RTA
RB
XIB
XOB/HFB
FFB
EFB
DATA
OUTPUTS
(QB
0
-QB
8
)
FLB/RTB
3966 drw 01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The AsyncFIFO™ is a trademark of Integrated Device Technology, Inc.
1. 内容简介 在2015年，苹果新一代的MacBook和Apple Watch皆搭载压力触控感应技术，它被Apple称为Force Touch，用户每次按下触控板之后除了可以在萤幕看见视觉回馈，它同时能够分辨出用户点按的力度强弱来做出一系列的相关操控与应用。而本文将介绍以HY16F184内建高精密Sigma-delta 24 Bit ADC搭配Uneo Force Sensor来实现一...[详细]
Arm 助力车厂将新车型上市时间至少提前一年。 Zena CSS 加速了软件和芯片开发进程，助力更快速、高效地交付 AI 功能。 作为预先验证且具备安全能力的计算平台，Zena CSS 能够节省约 20% 的工程资源，大幅降低开发的成本和复杂性。 未来几年，大多数汽车制造商将会基于 Zena CSS 产品系列进行开发 Arm 控股有限公司 近期宣布推出 Arm® Zena 计...[详细]
依托 Zena CSS 与 Arm 完整的合作伙伴生态，加速自动驾驶的落地进程。 闭上双眼，想象你正坐上车准备去上班。车内温度和座舱设置早已根据你的习惯调整到位。上车后，汽车通过学习已经了解你的驾乘习惯，主动询问你现在是否再次前往办公室。尽管你的车目前还无法在你居住的繁忙城区实现无监督导航，但你可以双手离开方向盘，让汽车在拥堵路段自主行驶，而你只需留意路况即可。 很快地，你的车就会提示你...[详细]
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
