INTEGRATED CIRCUITS
LF398
Sample-and-hold amplifier
Product data
Replaces LF198/LF298/LF398 of 1994 Aug 31
IC11
2001 Aug 03
Philips
Semiconductors
Philips Semiconductors
Product data
Sample-and-hold amplifier
LF398
DESCRIPTION
The LF398 is a monolithic sample-and-hold circuit which utilizes
high-voltage ion-implant JFET technology to obtain ultra-high DC
accuracy with fast acquisition of signal and low droop rate.
Operating as a unity gain follower, DC gain accuracy is 0.002%
typical and acquisition time is as low as 6
µs
to 0.01%. A bipolar
input stage is used to achieve low offset voltage and wide
bandwidth. Input offset adjust is accomplished with a single pin and
does not degrade input offset drift. The wide bandwidth allows the
LF398 to be included inside the feedback loop of 1 MHz op amps
without having stability problems. Input impedance of 10
10
Ω
allows
high source impedances to be used without degrading accuracy.
P-channel junction FETs are combined with bipolar devices in the
output amplifier to give droop rates as low as 5 mV/min with a 1
µF
hold capacitor. The JFETs have much lower noise than MOS
devices used in previous designs and do not exhibit high
temperature instabilities. The overall design guarantees no
feedthrough from input to output in the hold mode even for input
signals equal to the supply voltages.
Logic inputs are fully differential with low input current, allowing
direct connection to TTL, PMOS, and CMOS; differential threshold is
1.4 V. The LF398 will operate from
±5
V to
±18
V supplies. It is
available in 8-pin plastic DIP and 14-pin plastic SO packages.
PIN CONFIGURATIONS
N Package
1
2
3
4
TOP VIEW
8
7
6
5
V+
OFFSET VOLTAGE
INPUT
V–
LOGIC
LOGIC REFERENCE
C
h
OUTPUT
D Package
INPUT 1
NC 2
V– 3
NC 4
NC 5
NC 6
OUTPUT
7
TOP VIEW
14 V
OS
Adj
13 NC
12 V+
11 LOGIC
10 LOGIC REF
9
8
NC
C
h
FEATURES
•
Operates from
±5
V to
±18
V supplies
•
Less than 10
µs
acquisition time
•
TTL, PMOS, CMOS compatible logic input
•
0.5 mV typical hold step at C
H
= 0.01
µF
•
Low input offset
•
0.002% gain accuracy
•
Low output noise in hold mode
•
Input characteristics do not change during hold mode
•
High supply rejection ratio in sample or hold
•
Wide bandwidth
ORDERING INFORMATION
DESCRIPTION
14-Pin Plastic Small Outline (SO) Package
8-Pin Plastic Dual In-Line Package (DIP)
SL00083
Figure 1. Pin Configurations
APPLICATION
•
The LF398 is ideally suited for a wide variety of sample-and-hold
applications, including data acquisition, analog-to-digital
conversion, synchronous demodulation, and automatic test setup.
TEMPERATURE RANGE
0 to +70°C
0 to +70°C
ORDER CODE
LF398D
LF398N
DWG #
SOT108-1
SOT97-1
2001 Aug 03
2
853-0135 26832
Philips Semiconductors
Product data
Sample-and-hold amplifier
LF398
FUNCTIONAL DIAGRAM
OFFSET
TYPICAL APPLICATIONS
V+
30 kΩ
–
+
3
INPUT
8
LOGIC
LOGIC 7
REFERENCE
6
HOLD
CAPACITOR
300
Ω
SAMPLE 5 V
HOLD 0 V
LOGIC
INPUT
8
7
ANALOG INPUT
3
S/H
5
OUTPUT
1
4
5
6
C
h
OUTPUT
V–
SL00084
SL00085
Figure 2. Functional Diagram
Figure 3. Typical Applications
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
S
Supply voltage
Maximum power dissipation
T
amb
= 25
°C
(still-air)
3
N package
D package
T
amb
T
stg
V
IN
Operating ambient temperature range
Storage temperature range
Input voltage
Logic-to-logic reference differential voltage
2
Output short-circuit duration
Hold capacitor short-circuit duration
T
SOLD
Lead soldering temperature (10 sec max)
PARAMETER
RATING
±18
UNIT
V
1160
1040
0 to +70
-65 to +150
Equal to supply voltage
+7, -30
Indefinite
10
230
mW
mW
°C
°C
V
sec
°C
NOTES:
1. The maximum junction temperature of the LF398 is 150
°C.
When operating at elevated ambient temperature, the packages must be
derated based on the thermal resistance specified.
2. Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins must always be at least 2V
below the positive supply and 3 V above the negative supply.
3. Derate above 25
°C,
at the following rates:
N package at 9.3 mW/°C
D package at 8.3 mW/°C
2001 Aug 03
3
Philips Semiconductors
Product data
Sample-and-hold amplifier
LF398
DC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following conditions apply: unit is in “sample” mode; V
S
=
±15
V; T
j
= 25
°C;
–11.5 V3 V
IN
≤
+11.5 V;
C
H
= 0.01
µF;
and R
L
= 10 kΩ. Logic reference voltage = 0 V and logic voltage = 2.5 V.
SYMBOL
V
OS
I
BIAS
PARAMETER
In ut
Input offset voltage
4
In ut
Input bias current
4
Input impedance
Gain error
Feedthrough attenuation ratio at 1 kHz
Output im edance
Out ut impedance
“HOLD” step
2
I
CC
Supply current
4
Logic and logic reference input current
Leakage current into hold capacitor
4
t
AC
Acquisition time to 0.1%
0 1%
Hold capacitor charging current
Supply voltage rejection ratio
Differential logic threshold
TEST CONDITIONS
T
j
= 25
°C
Full temperature range
T
j
= 25
°C
Full temperature range
T
j
= 25
°C
T
j
= 25
°C,
R
L
=10 kΩ
Full temperature range
T
j
= 25
°C,
C
h
= 0.01
µF
T
j
= 25
°C,
“HOLD” mode
Full temperature range
T
j
= 25
°C,
C
h
= 0.01
µF,
V
OUT
= 0 V
T
j
≤
25
°C
T
j
= 25
°C
T
j
= 25
°C,
“HOLD” mode
∆V
OUT
= 10 V, C
h
= 1000 pF
C
h
= 0.01
µF
V
IN
–V
OUT
= 2 V
V
OUT
= 0 V
T
j
= 25
°C
80
0.8
1.0
4.5
2
30
4
20
5
110
1.4
2.4
80
90
0.5
4
6
2.5
6.5
10
200
Min
Typ
2
10
10
10
0.004
0.01
0.02
%
dB
Ω
mV
mA
µA
pA
µs
mA
dB
V
Max
7
10
50
100
UNIT
mV
nA
Ω
NOTES:
1. Unless otherwise specified, the following conditions apply. Unit is in “sample” mode, V
S
=
±15
V, T
j
= 25
°C,
–11.5 V
≤
V
IN
≤
+11.5 V,
C
h
= 0.01
µF,
and R
L
= 10 kΩ. Logic reference voltage = 0 V and logic voltage = 2.5 V.
2. Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an
additional 0.5 mV step with a 5 V logic swing and a 0.01
µF
hold capacitor. Magnitude of the hold step is inversely proportional to hold
capacitor value.
3. Leakage current is measured at a junction temperature of 25
°C.
The effects of junction temperature rise due to power dissipation or
elevated ambient can be calculated by doubling the 25
°C
value for each 11
°C
increase in chip temperature. Leakage is guaranteed over
full input signal range.
4. The parameters are guaranteed over a supply voltage of
±5
to
±18
V.
2001 Aug 03
4
Philips Semiconductors
Product data
Sample-and-hold amplifier
LF398
TYPICAL DC PERFORMANCE CHARACTERISTICS
Input Bias Current
25
20
15
CURRENT (mA)
10
5
0
–5
–10
–15
–50
–25
0
25
50
75
100
125 150
CURRENT (mA)
20
18
16
14
12
10
8
6
4
2
0
–50
–25
0
25
50
75
100
125 150
SINKING
SOURCING
Output Short Circuit Current
INPUT VOLTAGE — OUTPUT VOLTAGE (mV)
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
–15
–10
Gain Error
T
j
= 25
°C
R
L
= 10 kΩ
SAMPLE MODE
–5
0
5
10
15
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
INPUT VOLTAGE (V)
Hold Step
100
V+ = V– = 15 V
T
j
= 25
°C
10
HOLD STEP (mV)
CURRENT (nA)
10
100
Leakage Current Into
Hold Capacitor
2
V
S
=
±15
V
V
OUT
= 0 V
HOLD MODE
NORMALIZED HOLD STEP AMPLITUDE
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
–25
0
25
50
75
100
125 150
–15
Hold Step Input Voltage
T
j
= 100
°C
1
1
T
j
= 25
°C
0.1
10
–1
T
j
= 55
°C
0.01
100 pF
1000 pF
0.01
µF
0.1
µF
1
µF
10
–2
–50
–10
–5
0
5
10
15
HOLD CAPACITOR
JUNCTION TEMPERATURE (°C)
INPUT VOLTAGE (V)
SL00086
Figure 4. Typical DC Performance Characteristics
TYPICAL AC PERFORMANCE CHARACTERISTICS
Acquisition Time
1
V
IN
= 0 V to
±10
V
1%
10
TIME (
µ
s)
T
j
= 25
°C
250
V+ = V– = 15 V
225
200
TIME (ns)
0.1%
175
150
125
100
75
50
25
1000
0.001
0.01
HOLD CAPACITOR (µF)
0.1
0
–50
–25
0
25
50
POSITIVE
INPUT
STEP
0.1
75 100 125 150
0.1
1
10
100
1
MYLAR
TIME
CONSTANT
POLYPROPYLENE
AND POLYSTYRENE
HYSTERESIS
Aperture Time
100
Capacitor Hysteresis
MYLAR
HYSTERESIS
POLYPROPYLENE
AND POLYSTYRENE
TIME CONSTANT
∆V
OUT
≤
1 mV
∆V
IN
= 10 V
NEGATIVE
INPUT
STEP
10
0.01%
100
JUNCTION TEMPERATURE (°C)
SAMPLE TIME (ms)
SL00087
Figure 5. Typical AC Performance Characteristics
2001 Aug 03
5
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