AS5LC512K8
512K x 8 SRAM
3.3 VOLT HIGH SPEED SRAM with
CENTER POWER PINOUT
AVAILABLE AS MILITARY
SPECIFICATIONS
•MIL-STD-883 for Ceramic
•Extended Temperature Plastic (COTS)
SRAM
PIN ASSIGNMENT
(Top View)
36-Pin PSOJ (DJ)
36-Pin CLCC (EC)
FEATURES
• Ultra High Speed Asynchronous Operation
• Fully Static, No Clocks
• Multiple center power and ground pins for improved
noise immunity
• Easy memory expansion with CE\ and OE\
options
• All inputs and outputs are TTL-compatible
• Single +3.3V Power Supply +/- 0.3V
• Data Retention Functionality Testing
• Cost Efficient Plastic Packaging
• Extended Testing Over -55ºC to +125ºC for plastics
• RoHS Compliant Options Available
36-Pin Flat Pack (F)
OPTIONS
• Timing
10ns access
12ns access
15ns access
20ns access
25ns access
• Operating Temperature Ranges
883C (-55
o
C to +125
o
C)
Military (-55
o
C to +125
o
C)
Industrial (-40
o
C to +85
o
C)
• Package(s)
Ceramic Flatpack
Ceramic LCC
Plastic SOJ (400 mils wide)
• 2V data retention/low power*
MARKING
-10
-12
-15
-20
-25
/883C
/XT
/IT
F
EC
DJ
L
No. 307
No. 210
For more products and information
please visit our web site at
www.micross.com
AS5LC512K8
Rev. 2.4 10/13
Micross Components reserves the right to change products or specifications without notice.
1
AS5LC512K8
GENERAL DESCRIPTION
The AS5LC512K8 is a 3.3V high speed SRAM. It offers flex-
ibility in high-speed memory applications, with chip enable (CE\) and
output enable (OE\) capabilities. These features can place the outputs
in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write enable (WE\)
and CE\ inputs are both LOW. Reading is accomplished when WE\
remains HIGH and CE\ and OE\ go LOW.
SRAM
As a option, the device can be supplied offering a reduced power
standby mode, allowing system designers to meet low standby power
requirements. This device operates from a single +3.3V power supply
and all inputs and outputs are fully TTL-compatible.
The AS5LC512K8DJ offers the convenience and reliability of
the AS5LC512K8 SRAM and has the cost advantage of a plastic en-
capsulation. TSOPII with copper lead frames offers superior thermal
performance.
FUNCTIONAL BLOCK DIAGRAM
VCC
GND
INPUT BUFFER
ROW DECODER
1024 ROWS X
4096 COLUMNS
A0-A18
I/O
CONTROLS
4,194,304-BIT
MEMORY ARRAY
DQ8
DQ1
CE\
OE\
WE\
*POWER
DOWN
COLUMN DECODER
*On the low voltage Data Retention option.
PIN FUNCTIONS
A0 - A18
Address Inputs
Write Enable
Chip Enable
Output Enable
Data Inputs/Outputs
Power
Ground
No Connection
MODE
OE\ CE\ WE\
STANDBY
X
H
X
READ
L
L
H
NOT SELECTED H
L
H
WRITE
X
L
L
X = Don’t Care
TRUTH TABLE
WE\
I/O
HIGH-Z
Q
HIGH-Z
D
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
CE\
OE\
I/O
0
- I/O
7
V
CC
V
SS
NC
AS5LC512K8
Rev. 2.4 10/13
Micross Components reserves the right to change products or specifications without notice.
2
AS5LC512K8
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss
Vcc .........................................................................-.5V to 4.0V
Storage Temperature .....................................-65C to +150C
Short Circuit Output Current (per I/O)…........................20mA
Voltage on any Pin Relative to Vss........................-.5V to 4.6V
Maximum Junction Temperature**..............................+150C
Power Dissipation ................................................................1W
SRAM
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
** Junction temperature depends upon package type, cycle time,
loading, ambient temperature and airflow, and humidity.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
A
< +125
o
C & -40
o
C < T
A
< +85
o
C ; Vcc = 3.3V +0.3%)
DESCRIPTION
CONDITIONS
CE\ < V
IL
; Vcc = MAX
Power Supply
Current: Operating
f = MAX = 1/t
RC
Outputs Open
"L" Version Only
CE\ > V
IH
, All other inputs < V
IL
,
Vcc = MAX, f = 0,
Outputs Open
Power Supply
Current: Standby
"L" Version Only
CE\ > Vcc -0.2V; Vcc = MAX
V
IN
<Vss +0.2V or
V
IN
>Vcc -0.2V; f = 0
"L" Version Only
I
SBCLP
-
9
9
9
9
mA
I
CCSP
I
CCLP
90
80
70
60
55
mA
3, 2
-
60
50
40
35
mA
SYM
-10
-12
MAX
-15
-20
-25
UNITS NOTES
I
SBTSP
30
20
20
20
20
mA
I
SBTLP
I
SBCSP
-
15
15
15
15
mA
20
15
15
15
15
mA
µ
µ
CAPACITANCE
PARAMETER
Input Capacitance
Output Capactiance
AS5LC512K8
Rev. 2.4 10/13
CONDITIONS
T
A
= 25
o
C, f = 1MHz
V
IN
= 0
SYMBOL
C
I
Co
MAX
8
6
UNITS
pF
pF
NOTES
4
4
Micross Components reserves the right to change products or specifications without notice.
3
AS5LC512K8
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55
o
C < T
A
< +125
o
C or -40
o
C to +85
o
C; Vcc = 3.3V +0.3%)
DESCRIPTION
READ CYCLE
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold From Address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable Acess Time
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
WRITE CYCLE
WRITE Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Address Setup Time
Address Hold From End of Write
WRITE Pulse Width
Data Setup Time
Data Hold Time
Write Disable to Output in Low-Z
Write Enable to Output in High-Z
SYM
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
AOE
t
LZOE
t
HZOE
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP
t
DS
t
DH
t
LZWE
t
HZWE
10
8
8
0
0
8
6
1
2
5
0
4
12
8
8
0
0
10
6
1
2
5
2
2
4
4.5
0
6
15
10
10
0
0
12
7
1
2
6
-10
MIN
10
10
10
2
2
6
6
0
7
20
12
12
0
0
15
8
1
2
7
MAX
MIN
12
12
12
2
2
7
7
0
8
25
13
13
0
0
15
8
1
2
7
-12
MAX
MIN
15
15
15
2
2
8
8
0
9
-15
MAX
MIN
20
20
20
2
2
9
9
-20
MAX
MIN
25
25
25
-25
MAX
SRAM
UNITS NOTES
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 6, 7
4, 6, 7
4, 6, 7
4, 6, 7
4, 6, 7
4, 6, 7
AS5LC512K8
Rev. 2.4 10/13
Micross Components reserves the right to change products or specifications without notice.
4
AS5LC512K8
AC TEST CONDITIONS
Input pulse levels ................................................ Vss to 3.0V
Input rise and fall times .................................................. 3ns
Input timing reference levels ......................................... 1.5V
Output reference levels .................................................. 1.5V
Output load ............................................ See Figures 1 and 2
3.3V
R
L
= 50
Q
Z
O
=50
SRAM
319
V
L
= 1.5V
Q
353
5 pF
30 pF
Fig. 1 Output Load Equivalent
Fig. 2 Output Load Equivalent
NOTES
1. All voltages referenced to V
SS
(GND).
2. I
CC
limit shown is for absolute worst case switching of
ADDR, ADDR\, ADDR, etc.
3. I
CC
is dependent on output loading and cycle rates.
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
t
6. LZCE,
t
LZWE,
t
LZOE,
t
HZCE,
t
HZOE and
t
HZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV from steady state voltage.
7. At any given temperature and voltage condition,
t
HZCE is less than
t
LZCE, and
t
HZWE is less than
t
LZWE.
8. WE\ is HIGH for READ cycle.
9.
10.
11.
12.
13.
14.
15.
Device is continuously selected. Chip enables and
output enables are held in their active state.
Address valid prior to, or coincident with, latest
occurring chip enable.
t
RC = Read Cycle Time.
Chip enable and write enable can initiate and
terminate a WRITE cycle.
Output enable (OE\) is inactive (HIGH).
Output enable (OE\) is active (LOW).
ASI does not warrant functionality nor reliability of
any product in which the junction temperature
exceeds 150°C. Care should be taken to limit power to
acceptable levels.
DATA RETENTION ELECTRICAL CHARACTERISTICS
(L Version Only)
DESCRIPTION
Vcc for Retention Data
Data Retention Current
Chip Deselect to Data
Operation Recovery Time
AS5LC512K8
Rev. 2.4 10/13
CONDITIONS
CE\ > V
CC
-0.2V
V
IN
> V
CC
-0.2 or 0.2V
Vcc = 2.0V
SYM
V
DR
I
CCDR
t
CDR
t
R
MIN
2
MAX
UNITS
V
NOTES
6.5
0
20
mA
ns
ms
4
4, 11
Micross Components reserves the right to change products or specifications without notice.
5
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