September 2004
Preliminary Information
®
AS9C25256M2036L
AS9C25128M2036L
2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
Features
• True Dual-Port memory cells that allow simulta-
neous access of the same memory location
• Organisation: 262,144/131,072 x 36
[1]
• Fully Synchronous, independent operation on
both ports
• Selectable Pipeline or Flow-Through output
mode
• Fast clock speeds in Pipeline output mode: 250
MHz operation (18Gbps bandwidth)
• Fast clock to data access: 2.8ns for Pipeline out-
put mode
• Asynchronous output enable control
• Fast OE access times: 2.8ns
• Double Cycle Deselect (DCD) for Pipeline Out-
put Mode
• 18/17
[1]
-bit counter with Increment, Hold and
Repeat features on each port
• Dual Chip enables on both ports for easy depth
expansion
Note:
1. AS9C25256M2036L/AS9C25128M2036L
•
•
•
•
•
•
•
Interrupt and Collision Detection Features
2.5 V power supply for the core
LVTTL compatible, selectable 3.3V or
2.5V power supply for I/Os, addresses,
clock and control signals on each port
Snooze modes for each port for standby
operation
15mA typical standby current in power
down mode
Available in 256-pin Ball Grid Array
(BGA), 208-pin Plastic Quad Flatpack
(PQFP) and 208-pin fine pitch Ball Grid
Array (fpBGA)
Supports JTAG features compliant with
IEEE 1149.1
Selection guide
Feature
Minimum cycle time
Maximum Pipeline clock frequency
Maximum Pipeline clock access time
Maximum flow-through clock frequency
Maximum flow-through clock access time
Maximum operating current
Maximum snooze mode current
-250
4
250
2.8
150
6.5
TBD
18
-200
5
200
3.4
133
7.5
350
18
-166
6
166
3.6
100
10
300
18
-133
7.5
133
4.2
83
12
260
18
Units
ns
MHz
ns
MHz
ns
mA
mA
9/30/04; v.1.3
Alliance Semiconductor
P. 1 of 30
Copyright © Alliance Semiconductor. All rights reserved.
AS9C25256M2036L
AS9C25128M2036L
®
Dual port logic block diagram
R/W Control
R/W Control
BE3
A
-BE0
A
CE0
A
CE1
A
R/W
A
REGISTER BANK
D
Q
REGISTER BANK
D
Q
REGISTER BANK
Q
D
REGISTER BANK
Q
D
BE3
B
-BE0
B
CE0
B
CE1
B
R/W
B
O/P Control
O/P Control
O/P Control
O/P Control
1
1
0
PL/FT
0
PL/FT
PL/FT
A
OE
A
PL/FT
Qout
A
<35:0>
Qout
B
<35:0>
PL/FT
PL/FT
B
OE
B
REGISTER BANK
Q
D
REGISTER BANK
1
True Dual Port
Memory Array
256/128K X36
D
Q
REGISTER BANK
REGISTER BANK
DQ35
A
-DQ0
A
D
Q
Din
A
<35:0>
Din
B
<35:0>
Q
D
RPT
A
ADS
A
INC
A
A17
[1]A
-A0
A
Address
Decoding
Increment
Logic
Mirror
Register
REGISTER BANK
D
Q
Address
Decoding
REGISTER BANK
Q
D
Address Counter A
CE0
A
OPT
A
CLK
A
CE1
A
R/W
A
PL/FT
A
CLK
A
OPT
A
INT
A
COL
A
CE0
B
Address Counter B
Interrupt/Collision
Detection
Logic/Registers
CE1
B
R/W
B
PL/FT
B
CLK
B
OPT
B
INT
B
COL
B
OPT
B
CLK
B
ZZ
A
Snooze
Logic
Snooze
Logic
ZZ
B
TDI
TDO
TCK
JTAG
TMS
TRST
Note:
1. Address A17 is a NC for AS9C25128M2036L
9/30/04, v.1.3
Alliance Semiconductor
0
1
DQ35
B
-DQ0
B
RPT
B
ADS
B
INC
B
0
Increment
Logic
Mirror
Register
A17
[1]B
-A0
B
P. 2 of 30
AS9C25256M2036L
AS9C25128M2036L
®
General Description
The AS9C25256M2036L/AS9C25128M2036L is a high-speed CMOS 9/4.5-Mbit synchronous Dual-Port Static Random Access Memory
device, organized as 262,144/131,072 x 36 bits. It incorporates a selectable Flow-Through/Pipeline output feature for user flexibility. Clock-
to-data valid time is 2.8ns at 250 MHz for “Pipeline output” mode of operation.
Each port contains an 18/17 bit linear burst counter on the input address register that can loop through the whole address sequence. After
externally loading the counter with the initial address, it can be Incremented or Held for the next cycle. A new address can also be Loaded or
the “Previous Loaded” address can be re-accessed (Repeated) using counter controls (More description to follow). The Registers on control,
data, and address inputs provide minimal setup and hold times.
The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. A particular port can write
to a certain location while another port is reading from the same location, but the validity of read data is not guaranteed. However, the
reading port is informed about the possible collision through its collision alert signal. The result of writing to the same location by more than
one port at the same time is undefined.
The Asynchronous Output Enable input pin allows asynchronous disabling of output buffers at any given time. The Byte Enable inputs
allow individual byte read/write operations (refer Byte Control Truth Table). An automatic power down feature, controlled by CE0 and CE1,
permits the on-chip circuitry of each port to enter a very low standby power mode.
AS9C25256M2036L/AS9C25128M2036L can support an operating voltage of either 3.3V or 2.5V on either or both ports, which is
controlled by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V. This device is available in 256-pin Ball Grid
Array (BGA), 208-pin fine pitch Ball Grid Array (fpBGA) and 208-pin Plastic Quad Flatpack (PQFP)
Address Counter
The AS9C25256M2036L/AS9C25128M2036L carries an internal 18/17 bit address counter for each port which can loop through the entire
memory array. The Address counter features are discussed below:
Load:
Any required external address can be loaded on to the counter. This feature is similar to normal address load in conventional
memories.
Increment:
The address counter has the capability to internally increment the address value, potentially covering the entire memory array.
Once the whole address space is completed, the counter will wrap around. The address counter is not initailized on Power-up, hence a known
location has to be loaded before Increment operation.
Hold:
The value of the counter register can be held for an unlimited number of clock cycles by de-asserting ADS, INC, and RPT inputs.
Repeat:
The previously loaded address (loaded using a valid Load operation) can be re-accessed by asserting RPT input. A separate 18/17
bit register called “Mirror register” is used to hold the last loaded address.This register is not initialized on Power-up, hence a known
location has to be loaded before Repeat operation (Refer Counter control truth table for details).
9/30/04, v.1.3
Alliance Semiconductor
P. 3 of 30
AS9C25256M2036L
AS9C25128M2036L
®
Ball Assignment - 256-ball BGA
AS9C25256M2036L/AS9C25128M2036L
B - 256
Top view
1
A
NC
2
TDI
3
NC
4
A17
[1]A
NC
5
A14
A
A15
A
A13
A
6
A11
A
A12
A
A10
A
7
A8
A
A9A
8
BE2
A
BE3
A
BE1
A
9
CE1
A
CE0
A
BE0
A
10
OE
A
R/W
A
CLK
A
11
INC
A
RPT
A
ADS
A
12
A5
A
A4
A
A6
A
13
A2
A
A1
A
A3
A
VDD
14
A0
A
VDD
15
NC
16
NC
A
B
DQ18
A
NC
TDO
DQ17
A
NC
B
C
DQ18
B
DQ19
A
VSS
A16
A
A7
A
OPT
A
DQ17
B
DQ16
A
C
D
DQ20
B
DQ19
B
DQ20
A
PL/FT
A
VDDQ
A
VDDQ
A
VDDQ
B
VDDQ
B
VDDQ
A
VDDQ
A
VDDQ
B
VDDQ
B
DQ21
B
DQ21
A
DQ22
A
VDDQ
A
DQ23
A
DQ22
B
DQ23
B
VDDQ
A
DQ24
B
DQ24
A
DQ25
A
VDDQ
B
DQ26
A
DQ25
B
DQ26
B
VDDQ
B
DQ27
A
DQ28
B
DQ27
B
VDDQ
A
DQ29
B
DQ29
A
DQ28
A
VDDQ
A
DQ30
A
DQ31
B
DQ30
B
VDDQ
B
DQ32
B
DQ32
A
DQ31
A
VDDQ
B
VDD
VDD
INT
A
COL
A
VSS
VSS
VSS
VSS
VDD
VDD
DQ15
B
DQ15
A
DQ16
B
D
E
VDDQ
B
DQ13
A
DQ14
A
DQ14
B
VDDQ
B
DQ12
B
DQ13
B
DQ12
A
VDDQ
A
DQ10
A
DQ11
A
DQ11
B
VDDQ
A
DQ9
B
VDDQ
B
DQ8
B
VDDQ
B
DQ6
B
VDDQ
A
DQ5
A
VDDQ
A
DQ3
B
VDD
DQ2
A
DQ0
A
OPT
B
A0
B
DQ9
A
DQ7
B
DQ6
A
DQ4
B
DQ3
A
DQ1
B
DQ0
B
NC
DQ10
B
DQ8
A
DQ7
A
DQ5
B
DQ4
A
DQ2
B
DQ1
A
NC
E
F
VDD
NC
VSS
VSS
VSS
VSS
VDD
F
G
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G
H
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H
J
ZZ
B
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ZZ
A
VSS
J
K
VSS
VSS
VSS
VSS
VSS
VSS
K
L
VDD
NC
COL
B
INT
B
VSS
VSS
VSS
VSS
VDD
L
M
VDD
VDD
VSS
VSS
VSS
VDD
VDD
M
N
DQ33
A
DQ34
B
DQ33
B
PL/FT
B
VDDQ
B
VDDQ
B
VDDQ
A
VDDQ
A
VDDQ
B
VDDQ
B
VDDQ
A
VDDQ
A
DQ35
B
DQ34
A
DQ35
A
NC
NC
TMS
A16
B
NC
A13
B
A15
B
A14
B
A10
B
A12
B
A11
B
A7
B
A9
B
A8
B
BE1
B
BE3
B
BE2
B
BE0
B
CE0
B
CE1
B
CLK
B
R/W
B
OE
B
ADS
B
RPT
B
INC
B
A6
B
A4
B
A5
B
N
P
A3
B
A1
B
A2
B
P
R
TRST
R
T
TCK
NC
A17
[1]B
4
NC
NC
T
1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
Note:
1. Address A17 is a NC for AS9C25128M2036L
9/30/04, v.1.3
Alliance Semiconductor
P. 4 of 30
AS9C25256M2036L
AS9C25128M2036L
®
Ball Assignment - 208-ball fpBGA
1
A
2
3
VSS
4
TDO
5
COL
A
6
A16
A
7
A12
A
A9
A
A10
A
A7
A
8
A8
A
BE2
A
BE3
A
BE0
A
9
BE1
A
CE0
A
CE1
A
VDD
10
VDD
11
CLK
A
ADS
A
R/W
A
RPT
A
12
INC
A
A5
A
A6
A
A3
A
13
A4
A
A1
A
A2
A
VDD
14
A0
A
NC
15
OPT
A
16
DQ17
A
17
VSS
A
DQ19
A
DQ18
A
DQ20
B
VSS
B
DQ18
B
TDI
A17
[1]A
A13
A
INT
A
A15
A
A14
A
A11
A
VSS
VDDQ
B
DQ16
A
DQ15
B
DQ16
B
DQ15
A
VSS
B
C
VDDQ
A
DQ19
B
VDDQ
B
PL/FT
A
DQ22
A
VSS
DQ21
A
DQ20
A
VSS
VDD
C
D
OE
A
DQ17
B
VDDQ
A
DQ14
A
DQ14
B
DQ12
A
DQ13
B
VSS
VSS
DQ13
A
D
E
DQ23
A
DQ22
B
VDDQ
B
DQ21
B
VDDQ
A
DQ23
B
DQ24
A
DQ26
A
VDD
VSS
VSS
E
F
DQ12
B
DQ11
A
VDDQ
B
F
G
DQ25
A
DQ24
B
DQ9
A
VDDQ
A
DQ10
A
DQ11
B
VDD
DQ9
B
VDD
VSS
DQ10
B
VDDQ
B
VSS
G
H
DQ26
B
VDDQ
B
DQ25
B
VSS
ZZ
B
VSS
H
J
VDDQ
A
VDD
DQ28
B
VSS
K
DQ27
B
AS9C25256M2036L/AS9C25128M2036L
F - 208
Top view
ZZ
A
VSS
J
DQ7
B
VDDQ
A
DQ8
B
DQ6
B
VSS
DQ7
A
DQ6
A
VSS
K
L
DQ29
B
DQ28
A
VDDQ
B
DQ27
A
VDDQ
A
DQ29
A
DQ30
B
DQ31
A
VSS
VSS
DQ8
A
L
M
DQ5
B
VDDQ
B
DQ5
A
DQ4
A
M
N
DQ31
B
DQ30
A
TRST
A16
B
A12
B
A9
B
A10
B
A7
B
A8
B
BE2
B
BE3
B
BE0
B
BE1
B
CE0
B
CE1
B
VDD
VDD
CLK
B
ADS
B
R/W
B
RPT
B
INC
B
A5
B
A6
B
A3B
A4
B
A1
B
A2
B
A0
B
DQ3
B
VDDQ
A
DQ4
B
DQ2
A
NC
DQ3
A
VSS
N
P
DQ32
B
DQ32
A
VDDQ
B
DQ35
B
VSS
DQ33
A
DQ34
B
TCK
P
R
A17
[1]B
A13
B
INT
B
A15
B
A14
B
A11
B
VSS
VDDQ
A
DQ1
B
VDDQ
B
DQ0
B
OPT
B
VSS
DQ2
B
DQ1
A
R
T
DQ33
B
DQ34
A
VDDQ
A
TMS
VSS
DQ35
A
PL/FT
B
COL
B
VSS
VSS
T
U
OE
B
VDD
DQ0
A
U
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Note:
1. Address A17 is a NC for AS9C25128M2036L
9/30/04, v.1.3
Alliance Semiconductor
P. 5 of 30
为我们提建议&公告
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
