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IC61S25636D-250BI

产品描述Standard SRAM, 256KX36, 3ns, CMOS, PBGA119,
产品类别存储    存储   
文件大小328KB,共22页
制造商Integrated Circuit Solution Inc
下载文档 详细参数 全文预览

IC61S25636D-250BI概述

Standard SRAM, 256KX36, 3ns, CMOS, PBGA119,

IC61S25636D-250BI规格参数

参数名称属性值
是否Rohs认证不符合
Objectid104486845
包装说明BGA, BGA119,7X17,50
Reach Compliance Codeunknown
ECCN代码3A991.B.2.A
最长访问时间3 ns
最大时钟频率 (fCLK)250 MHz
I/O 类型COMMON
JESD-30 代码R-PBGA-B119
JESD-609代码e0
内存密度9437184 bit
内存集成电路类型STANDARD SRAM
内存宽度36
端子数量119
字数262144 words
字数代码256000
工作模式SYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织256KX36
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码BGA
封装等效代码BGA119,7X17,50
封装形状RECTANGULAR
封装形式GRID ARRAY
并行/串行PARALLEL
认证状态Not Qualified
最大待机电流0.1 A
最小待机电流3.14 V
最大压摆率0.41 mA
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn/Pb)
端子形式BALL
端子节距1.27 mm
端子位置BOTTOM

IC61S25636D-250BI文档预览

IC61S25632T/D IC61S25636T/D
IC61S51218T/D
Document Title
8Mb SyncBurst Pipelined SRAM
Revision History
Revision No
0A
0B
History
Initial Draft
1. Move the
FT
pin for user-configurable Flow
throught or pipelineed operation, That pin can be
NC or connected to V
CC
for pipelined operation.
Refer to Pin configuration.
2. Revise the power supply charaetoristics at page 12
3. Resive the t
KQ
of 250 MHZ from 2.5ns to 3ns.
4. Move the 100 MHZ speed grade.
Draft Date
Remark
September 24,2001
August 13,2002
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
1
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
256K x 32, 256K x 36, 512K x 18
8Mb S/DCD SYNCBURST Pipelined SRAMs
FEATURES
Pipeline Mode operation
Single/Dual Cycl Deselect
User-selectable Output Drive Strength with XQ Mode
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and control
Pentium™ or linear burst sequence control using
MODE input
Common data inputs and data outputs
JEDEC 100-Pin TQFP and 119-pin PBGA package
Single +3.3V, +10%, –5% core power supply
Power-down snooze mode
2.5V or 3.3V I/O Supply
Snooze MODE for reduced-power standby
T version (three chip selects)
D version (two chip selects)
Controls
All synchronous inputs pass through registers controlled by a
positive-edge-triggered single clock input.Bursts can be initiated
with either
ADSP
(Address Status Processor) or
ADSC
(Address
Status Cache Controller) input pins. Subsequent burst ad-
dresses can be generated internally and controlled by the
ADV
(burst address advance) input pin. The mode pin is used to select
the burst sequence order, Linear burst is achieved when this pin
is tied LOW. Interleave burst is achieved when this pin is tied
HIGH or left floating.
SCD and DCD Pipelined Reads
The device is a SCD (Single Cycle Deselect) and DCD(Dual
Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs
pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input on Bump 4L.
Byte Write and Global Write
Write cycles are internally self-timed and are initiated by the rising
edge of the clock input. Write cycles can be from one to four bytes
wide as controlled by the write control inputs.Separate byte
enables allow individual bytes to be written. Byte write operation
is performed by using byte write enable (BWE).input combined
with one or more individualbyte write signals (BWx). In addition,
Global Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
IOL/IOH Drive strength Options
The XQ pin allows selection between high drive strength (XQ
low) for multi-drop bus applications and normal drive strength
(XQ floating or high) point-to-point applications. See the Output
Driver Characteristics chart for details.
Snooze Mode
Low power (Snooze mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK). Memory
data is retained during Snooze mode.
DESCRIPTION
ICSI's 8Mb SyncBurst Pipelined SRAMs integrate a 512k
x 18, 256k x 32, or 256k x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst counter.
Applications
The ICSI SyncBurst Pipelined SRAM family employs
high-speed ,low-power CMOS designs that are fabricated
using an advanced CMOS process to provide Level 2
Cache applications supporting Pentium and PowerPC
microprocessors originally, the device now finds applica-
tion ranging from DSP main store to networking chip set
support.
FAST ACCESS TIME
Pipeline
3-1-1-1
Symbol
t
KQ
t
KC
I
CC
1
-250
3
4
390
-200
3.1
5
360
-166
3.5
6
330
-133
4
7.5
300
Units
ns
ns
mA
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
BLOCK DIAGRAM
MODE
Q0
A0'
CLK
CLK
A0
BINARY
COUNTER
ADV
ADSC
ADSP
Q1
A1'
A1
256Kx32; 256Kx36;
512Kx18
MEMORY ARRAY
18/19
16/17
D
Q
18/19
An-A0
ADDRESS
REGISTER
CLK
32, 36,
or 18
32, 36,
or 18
GW
BWE
BWd
(x32/x36)
DQd
BYTE WRITE
REGISTERS
CLK
D
Q
BWb
(x32/x36)
DQc
Q
BYTE WRITE
REGISTERS
CLK
D
BWa
(x32/x36/x18)
DQb
BYTE WRITE
REGISTERS
CLK
D
Q
BWa
(x32/x36/x18)
DQa
Q
BYTE WRITE
REGISTERS
D
CLK
(T, D)CE
(T, D) CE2
(T) CE
2
D
Q
4
ENABLE
REGISTER
CLK
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
OE
32, 36,
or 18
DQa - DQd
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
3
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIN CONFIGURATION
119-pin PBGA (Top View)
1
A
VCCQ
B
NC
C
NC
D
DQc1
E
DQc2
F
VCCQ
G
DQc5
H
DQc7
J
VCCQ
K
DQd1
L
DQd4
M
VCCQ
N
DQd6
P
DQd8
R
NC
T
NC
U
VCCQ
NC
NC
NC
NC
NC
VCCQ
NC
SA
SA
SA
NC
ZZ
SA
MODE
VCC
NC
SA
NC
NC
GND
A0
GND
NC
DQa1
DQd7
GND
A1
GND
DQa3
DQa2
DQd5
GND
BWE
GND
DQa4
VCCQ
DQd3
BWd
SCD
BWa
DQa5
DQa6
DQd2
GND
CLK
GND
DQa7
DQa8
VCC
NC
VCC
NC
VCC
VCCQ
DQc8
GND
GW
GND
DQb2
DQb1
DQc6
BWc
ADV
BWb
DQb4
DQb3
DQc4
GND
OE
GND
DQb5
VCCQ
DQc3
GND
CE
GND
DQb6
DQb7
NC
GND
XQ
GND
NC
DQb8
SA
SA
VCC
SA
SA
NC
CE2
SA
ADSC
SA
SA
NC
SA
SA
ADSP
SA
SA
VCCQ
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
XQ
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
100-Pin TQFP (D Version)
SA
SA
CE
CE2
BWd
BWc
BWb
BWa
SA
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
SA
SA
2
3
4
5
6
7
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE
SA
SA
SA
SA
A1
A0
NC
NC
GND
VCC
NC
NC
A10
SA
SA
SA
SA
SA
SA
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
SCD
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
256K x 32
Note:Ball R5 connecting to V
CC
is acceptable
Note:pin 14 connecting to V
CC
is acceptable
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
DQa-DQd
MODE
SCD
XQ
V
CC
GND
V
CCQ
ZZ
Synchronous Data Input/Output
Burst Sequence Mode Selection
Single Cycle Deselect/Dual Cycle
Deselect Mode Control
Output Drive Control
+3.3V Power Supply
Ground
Isolated Output Buffer Supply : +3.3V
or 2.5V
Snooze Enable
A2-A17
CLK
ADSP
ADSC
ADV
BWa
-BWd
BWE
GW
CE
, CE2
OE
4
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIN CONFIGURATION
100-Pin TQFP (T Version)
SA
SA
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
SA
SA
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
XQ
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE
SA
SA
SA
SA
A1
A0
NC
NC
GND
VCC
NC
SA
SA
SA
SA
SA
SA
SA
SA
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
SCD
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
256K x 32
Note:Pin 14 connecting to Vcc is acceptable
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
DQa-DQd
MODE
SCD
XQ
V
CC
GND
V
CCQ
ZZ
Synchronous Data Input/Output
Burst Sequence Mode Selection
Single Cycle Deselect/Dual Cycle
Deselect Mode Control
Output Drive Control
+3.3V Power Supply
Ground
Isolated Output Buffer Supply : +3.3V
or 2.5V
Snooze Enable
A2-A17
CLK
ADSP
ADSC
ADV
BWa
-BWd
BWE
GW
CE,CE2,CE2
OE
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
5
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