ADC-HX, ADC-HZ Series
12-Bit, 8 and 20µsec
Analog-to-Digital Converters
FEATURES
•
•
•
•
•
•
12-bit resolution
8 or 20 microsecond conversion times
5 input voltage ranges
Internal high Z input buffer
Short-cycle operation
MIL-STD-883 models available
®
®
INNOVATION and EXCELLENCE
GENERAL DESCRIPTION
The ADC-HX and ADC-HZ Series are self-contained, high-
performance, 12-bit A/D converters manufactured with thick
and thin-film hybrid technology. They use the successive
approximation conversion technique to achieve a 12-bit
conversion in 20 and 8 microseconds, respectively. Five input
voltage ranges are programmable by external pin connection.
An internal buffer amplifier is also provided for applications in
which 50 megohm input impedance is required.
These converters utilize a fast 12-bit monolithic DAC which
includes a precision zener reference source. The circuit also
contains a fast monolithic comparator, a monolithic 12-bit
successive approximation register, a clock and a monolithic
buffer amplifier. Nonlinearity is specified at ±1/2LSB maximum.
Both models have identical operation except for conversion
speed. They can be short-cycled to give faster conversions in
lower-resolution applications. Use of the internal buffer
amplifier increases conversion time by 3 microseconds, the
settling time of the amplifier. Output coding is complementary
binary, complementary offset binary, or complementary two’s
complement. Serial data is also brought out. The package is a
32-pin ceramic TDIP. Models are available for use in either
commercial (0 to +70°C) or military (–55 to +125°C) operating
INPUT/OUTPUT CONNECTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FUNCTION
BIT 12 (LSB)
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1 (MSB)
BIT 1 (MSB)
SHORT CYCLE
DIGITAL COMMON
+5V POWER
PIN
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
FUNCTION
SERIAL DATA OUTPUT
–15V POWER
BUFFER INPUT
BUFFER OUTPUT
+15V POWER
GAIN ADJUST
ANALOG COMMON
20V INPUT RANGE
10V INPUT RANGE
BIPOLAR OFFSET
COMPARATOR INPUT
START CONVERT
E.O.C. (STATUS)
CLOCK OUT
REFERENCE OUT
CLOCK RATE
temperature ranges. MIL-STD-883 and DESC Standard
Military Drawing models are also available.
+15V POWER
28
–15V POWER
31
BUFFER
AMPLIFIER
6.3kW
REF. OUT
18
+5V POWER
16
BUFFER 30
INPUT
+
PRECISION
REF (+6.3V)
GAIN
27 ADJUST
BUFFER 29
OUTPUT
BIPOLAR
23
OFFSET
COMPARATOR 22
INPUT
5kW
10V
24
INPUT
5kW
20V
25
INPUT
ANALOG
26
COMMON
CLOCK
SUCCESSIVE
APPROXIMATION
REGISTER
COMPARATOR
14 SHORT
CYCLE
20
E.O.C.
STATUS
12-BIT DAC
15
DIGITAL
COMMON
17
CLOCK
RATE
19
CLOCK
OUT
21
START
CONV.
1
2
3
10
4
9
5
8
6
7
7
6
8
5
9 10 11 12
4
3
2
13
1
12 11
LSB.
1
BIT NO.
MSB MSB
32
SERIAL
DATA
OUT
PARALLEL DATA OUT
Figure 1. Functional Block Diagram
2-1
DATEL, Inc.,
11 Cabot Boulevard, Mansfield, MA 02048-1194 (U.S.A.) Tel: 508-339-3000 Fax: 508-339-6356 • For immediate assistance 800-233-2765
®
®
ADC-HX, ADC-HZ
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
+15V Supply, Pin 28
–15V Supply, Pin 31
+5V Supply, Pin 16
Digital Inputs, Pins 14, 21
Analog Inputs, Pins 24, 25
Buffer Input, Pin 30
Lead Temperature (10 seconds)
LIMITS
+18
–18
+7
±5.5
±25
±15
300
UNITS
Volts
Volts
Volts
Volts
Volts
Volts
°C
POWER REQUIREMENTS
Power Supply Voltages
+15V ±0.5V at +20mA
–15V ±0.5V at –25mA
+5V ±0.25V at +85mA
PHYSICAL/ENVIRONMENTAL
Operating Temp. Range, Case
Storage Temperature Range
Package Type
Weight
Thermal Impedance
θ
JC
θ
JA
0 to +70°C or –55 to +125°C
–65 to +150°C
32-pin ceramic TDIP
0.5 ounces (14 grams)
6°C/W
30°C/W
FUNCTIONAL SPECIFICATIONS
(Typical at +25°C and ±15V and +5V supplies unless otherwise noted)
INPUTS
Analog Input Ranges
Unipolar
Bipolar
Input Impedance
Input Impedance with Buffer
Input Bias Current of Buffer
Start Conversion
ADC-HX12B
ADC-HZ12B
0 to +5V, 0 to +10V
±2.5V, ±5V, ±10V
2.5k (0 to +5V, ±2.5V)
5k (0 to +10V, ±5V)
10k (±10V)
50 megohms
125nA typical, 250nA max.
+2V min. to +5.5V max. positive pulse with dur-
ation of 100ns min. Rise and fall times <30ns.
Logic "1" to "0" transition resets converter and
initiates next conversion. Loading: 2 TTL loads.
Footnotes:
➀
Adjustable to zero.
➁
FSR is full scale range and is 10V for 0 to +10V or ±5V inputs and 20V for
±10V input, etc.
➂
Without buffer amplifier used. ADC-HZ may require external adjustment
of clock rate.
➃
Short cycled operation.
➄
All digital outputs can drive 2 TTL loads.
TECHNICAL NOTES
1. It is recommended that the ±15V power input pins both be
bypassed to ground with a 0.01µF ceramic capacitor in
parallel with a 1µF electrolytic capacitor and the +5V power
input pin be bypassed to ground with a 10µF electrolytic
capacitor as shown in the connection diagrams. In addition,
GAIN ADJUST (pin 27) should be bypassed to ground with
a 0.01µF ceramic capacitor. These precautions will assure
noise free operation of the converter.
2. DIGITAL COMMON (pin 15) and ANALOG COMMON
(pin 26) are not connected together internally, and therefore
must be connected as directly as possible externally. It is
recommended that a ground plane be run underneath the
case between the two commons. Analog ground and ±15V
power ground should be run to pin 26 whereas digital
ground and +5V ground should be run to pin 15.
3. External adjustment of zero or offset and gain are made by
using trimming potentiometers connected as shown in the
connection diagrams. The potentiometer values can be
between 10k and 100k Ohms and should be 100ppm/°C
cermet types. The trimming pots should be located as close
as possible to the converter to avoid noise pickup. In some
cases, for example 8-bit short-cycled operation, external
adjustment may not be necessary.
4. Short-cycled operation results in shorter conversion times
when the conversion is truncated to less than 12 bits. This
is done by connecting SHORT CYCLE (pin 14) to the
output bit following the last bit desired. For example, for an
8-bit conversion, pin 14 is connected to the bit 9 output.
Maximum conversion times are given for short-cycled
conversions of 8 or 10 bits. In these two cases, the clock
rate is accelerated by connecting the CLOCK RATE adjust
(pin 17) to +5V (10 bits) or +15V (8 bits). The clock rate
should not be arbitrarily speeded up to exceed the
maximum conversion rate at a given resolution, as missing
codes will result.
PERFORMANCE
Resolution
Nonlinearity
Differential Nonlinearity
Accuracy Error
➀
Gain (before adjustment)
Zero, Unipolar (before adj.)
Offset, Bipolar (before adj.)
Temperature Coefficient
Gain
Zero, Unipolar
Offset, Bipolar
Diff. Nonlinearity Tempco
No Missing Codes
Conversion Time
➂
12 Bits
10 Bits
➃
8 Bits
➃
Buffer Settling Time
(10V step)
Power Supply Rejection
OUTPUTS
➄
Parallel Output Data
12 parallel lines of data held until next
conversion command.
V
OUT
("0")
≤
+0.4V
V
OUT
("1")
≥
+2.4V
Complementary binary
Complementary offset binary
Complementary two’s complement
NRZ successive decision pulses out, MSB first.
Compl. binary or compl. offset binary coding.
Conversion status signal. Output is logic "1"
during reset and conversion and logic "0"
when conversion complete.
Train of positive going +5V 100ns pulses.
600kHz for ADC-HX and 1.5MHz for
ADC-HZ (pin 17 grounded).
+6.3V
±20ppm/°C max.
2.5mA max.
12 bits
±1/2LSB max.
±3/4LSB max.
±0.2%
±0.1% of FSR
➁
±0.2% of FSR
➁
±20ppm/°C max.
±5ppm/°C of FSR max.
➁
±10ppm/°C of FSR max.
➁
±2ppm/°C of FSR max.
➁
Over opererating temperature range
20µs max.
15µs max.
10µs max.
3µs to ±0.01%
±0.004%/% supply max.
8µs max.
6µs max.
4µs max.
Unipolar Coding
Bipolar Coding
Serial Output Data
End of Conversion (Status)
Clock Output
Internal Reference
Reference Tempco
External Reference Current
DATEL, Inc.,
11 Cabot Boulevard, Mansfield, MA 02048-1194 (U.S.A.) Tel: 508-339-3000 Fax: 508-339-6356 • For immediate assistance 800-233-2765
®
®
ADC-HX, ADC-HZ
5. Note that output coding is complementary coding. For
unipolar operation it is complementary binary, and for
bipolar operation it is complementary offset binary or
complementary two’s complement. In cases in which
bipolar coding of offset binary or two’s complement is
required, this can be achieved by inverting the analog input
to the converter (using an op amp connected for gain of –1).
The converter is then calibrated so that –FS analog input
gives an output code of 0000 0000 0000, and +FS – 1LSB
gives 1111 1111 1111.
6. These converters can be operated with an external clock.
To accomplish this, a negative pulse train is applied to
START CONVERT (pin 21). The rate of the external clock
must be lower than the rate of the internal clock as adjusted
(see Short Cycle Operation tables) for the converter
resolution selected. The pulse width of the external clock
should be between 100 and 300 nanoseconds. Each N-bit
conversion cycle requires a pulse train of N + 1 clock pulses
for completion, e.g., an 8-bit conversion requires 9 clock
pulses for completion. A continuous pulse train may be
used for consecutive conversions, resulting in an N-bit
conversion every N + 1 pulses, or the E.O.C. output may be
used to gate a continuous pulse train for single conversions.
7. When the input buffer amplifier is used, a delay equal to its
settling time must be allowed between the input level change,
such as a multiplexer channel change, and the negative-
going edge of the START CONVERT pulse. If the buffer is
not required, BUFFER INPUT (pin 30) should be tied to
ANALOG COMMON (pin 26). This prevents the unused
amplifier from introducing noise into the converter. For
applications not using the buffer, the converter must be driven
from a source with an extremely low output impedance.
CODING TABLE
UNIPOLAR OPERATION
COMP.
BINARY CODING
MSB
0000
0001
0011
0111
1011
1101
1111
1111
0000
1111
1111
1111
1111
1111
1111
1111
LSB
0000
1111
1111
1111
1111
1111
1110
1111
CODING TABLE
BIPOLAR OPERATION
COMP.
OFFSET BINARY
MSB
0000
0001
0011
0111
1011
1101
1111
1111
0000
1111
1111
1111
1111
1111
1111
1111
LSB
0000
1111
1111
1111
1111
1111
1110
1111
COMP. TWO’S
COMPLEMENT
MSB
1000
1001
1011
1111
0011
0101
0111
0111
0000
1111
1111
1111
1111
1111
1111
1111
LSB
0000
1111
1111
1111
1111
1111
1110
1111
INPUT RANGE
0 to +10V
+9.9976V
+8.7500
+7.5000
+5.0000
+2.5000
+1.2500
+0.0024
0.0000
0 to +5V
+4.9988V
+4.3750
+3.7500
+2.5000
+1.2500
+0.6250
+0.0012
0.0000
INPUT VOLTAGE RANGE
±10V
+9.9951V
+7.5000
+5.0000
0.0000
–5.0000
–7.5000
–9.9951
–10.0000
±5V
+4.9976V
+3.7500
+2.5000
0.0000
–2.5000
–3.7500
–4.9976
–5.0000
±2.5V
+2.4988V
+1.8750
+1.2500
0.0000
–1.2500
–1.8750
–2.4988
–2.5000
SHORT CYCLE OPERATION
Refer to Technical Note 4 for methods of reducing the ADC-HX or ADC-HZ conversion times.
CONNECTIONS
8, 10 & 12-BIT CONVERSION TIMES
RESOLUTION
12 BITS
20µs
8µs
17 & 15
14 & 16
10 BITS
15µs
6µs
17 & 16
14 & 2
8 BITS
10µs
4µs
17 & 28
14 & 4
16
15
14
SHORT
CYCLE
17
CLOCK
RATE
+5V
+15V
ADC-HX Conversion Time
ADC-HZ Conversion Time
Connect These
Pins Together
TO SELECTED
DATA OUTPUT PIN
PIN 14 CONNECTION
RES. (BITS)
1
2
3
4
5
6
PIN 14 TO
PIN 11
PIN 10
PIN 9
PIN 8
PIN 7
PIN 6
RES. (BITS)
7
8
9
10
11
12
PIN 14 TO
PIN 5
PIN 4
PIN 3
PIN 2
PIN 1
PIN 16
CLOCK RATE VS. VOLTAGE
PIN 17
VOLTAGE
0V
+5V
+15V
CLOCK RATE
ADC-HX
600kHZ
720kHZ
880kHz
ADC-HZ
1.5MHZ
1.8MHz
2.2MHz
Analog-to-Digital Converters
®
®
ADC-HX, ADC-HZ
START
CONVERT IN
+
10µF
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
0.01
µF
0.01µF CAPS ARE CERAMIC TYPES
–15V
+5V
+15V
ZERO
ADJUST
2.2MW
10kW
TO
100kW
+5V COMMON
DATA
OUTPUTS
ADC-HX
OR
ADC-HZ
ANALOG INPUT
(–5 TO +5V)
15V
COMMON
0.01µF
+
2.8MW
GAIN
ADJUST
0.01
µF
10kW
TO
100kW
+
1µF
CAP
Figure 2. Bipolar Operation, –5 to +5V
+5V
+
10µF
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1µF
CAP
START
CONVERT IN
+15V
OFFSET
ADJUST
2.2MW
10kW
TO
100kW
+5V COMMON
DATA
OUTPUTS
ADC-HX
OR
ADC-HZ
ANALOG INPUT
(0 TO +10V)
15V
COMMON
0.01µF
+
2.8MW
GAIN
ADJUST
0.01
µF
0.01
µF
10kW
TO
100kW
–15V
+
0.01µF CAPS ARE CERAMIC TYPES
Figure 3. Unipolar Operation, 0 to +10V
CONNECTIONS AND CALIBRATION
INPUT CONNECTIONS
WITHOUT BUFFER
INPUT VOLTAGE
RANGE
0 to +5V
0 to +10V
±2.5V
±5V
±10V
INPUT
PIN
24
24
24
24
25
CONNECT THESE
PINS TOGETHER
22 & 25
—
22& 25
—
—
23 & 26
23 & 26
23 & 22
23 & 22
23 & 22
INPUT
PIN
30
30
30
30
30
WITH BUFFER
CONNECT THESE
PINS TOGETHER
22 & 25
—
22 & 25
—
—
23 & 26
23 & 26
23 & 22
23 & 22
23 & 22
29 & 24
29 & 24
29 & 24
29 & 24
29 & 25
DATEL, Inc.,
11 Cabot Boulevard, Mansfield, MA 02048-1194 (U.S.A.) Tel: 508-339-3000 Fax: 508-339-6356 • For immediate assistance 800-233-2765
®
®
ADC-HX, ADC-HZ
CALIBRATION PROCEDURE
1. Connect the converter for bipolar or unipolar operation.
Use the input connection table for the desired input voltage
range and input impedance. Apply START CONVERT
pulses of 100 nanoseconds minimum duration to pin 21.
The spacing of the pulses should be no less than the
maximum conversion time.
2.
Zero and Offset Adjustments
Apply a precision voltage reference source between the
selected analog input and ground. Adjust the output of the
reference source to the value shown in the Calibration Table
for the unipolar zero adjustment (zero + 1/2LSB) or the
bipolar offset adjustment (–FS + 1/2LSB). Adjust the
trimming potentiometer so that the output code flickers
equally between 1111 1111 1111 and 1111 1111 1110.
3.
Full Scale Adjustment
Change the output of the precision voltage reference source
to the value shown in the Calibration Table for the unipolar
or bipolar gain adjustment (+FS – 1.5LSB). Adjust the gain
trimming potentiometer so that the output code flickers
equally between 0000 0000 0001 and 0000 0000 0000.
CALIBRATION TABLE
RANGE
UNIPOLAR
0 to +5V
0 to +10V
BIPOLAR
±2.5V
±5V
±10V
ADJUST.
Zero
Gain
Zero
Gain
Offset
Gain
Offset
Gain
Offset
Gain
INPUT VOLTAGE
+0.6mV
+4.9982V
+1.2mV
+9.9963V
–2.4994V
+2.4982V
–4.9988V
+4.9963V
–9.9976V
+9.9927V
TIMING DIAGRAM FOR
ADC-HX, ADC-HZ OUTPUT: 101010101010
1
START
CONVERT
100ns min.
0
60ns
E.O.C.
(STATUS)
40ns
100ns
CLOCK
OUT
40ns
SERIAL
DATA OUT
BIT 1
(MSB)
BIT 2
BIT 3
40ns
1
BIT 1
(MSB)
0
1
BIT 2
0
1
BIT 3
0
BIT 12
(LSB)
1
0
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10 BIT 11
BIT 12
(LSB)
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
1
T1
PARALLEL DATA
NOW VALID
0
50ns
1
0
T2
TIMING DIAGRAM
OPERATING PERIODS
ADC-HX
T
1
T
2
20µs
1.56µs
ADC-HZ
8µs
0.56µs
Analog-to-Digital Converters
单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
