Datasheet> 器件分类 > 存储> 存储> IS61VF25636B-7.5B3I

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IS61VF25636B-7.5B3I: 产品描述Cache SRAM, 256KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, TFBGA-165; 产品类别存储存储; 文件大小824KB，共33页; 制造商ISSI(芯成半导体); 官网地址http://www.issi.com/

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IS61VF25636B-7.5B3I概述

Cache SRAM, 256KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, TFBGA-165

IS61VF25636B-7.5B3I规格参数

参数名称	属性值
Objectid	8141454107
包装说明	TBGA,
Reach Compliance Code	unknown
Country Of Origin	Mainland China, Taiwan
ECCN代码	3A991.B.2.A
YTEOL	5.75
最长访问时间	7.5 ns
JESD-30 代码	R-PBGA-B165
长度	15 mm
内存密度	9437184 bit
内存集成电路类型	CACHE SRAM
内存宽度	36
功能数量	1
端子数量	165
字数	262144 words
字数代码	256000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	256KX36
封装主体材料	PLASTIC/EPOXY
封装代码	TBGA
封装形状	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE
并行/串行	PARALLEL
座面最大高度	1.2 mm
最大供电电压 (Vsup)	2.625 V
最小供电电压 (Vsup)	2.375 V
标称供电电压 (Vsup)	2.5 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
宽度	13 mm

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IS61(64)LF25636B, IS61VF/VVF25636B

IS61(64)LF51218B, IS61VF/VVF51218B

256K x 36, 512K x 18

9 Mb SYNCHRONOUS

FLOW-THROUGH

STATIC RAM

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth expan-

sion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for BGA package

• Power Supply

LF: Vdd

3.3V (+

5%), Vddq

3.3V/2.5V (+

5%)

VF: Vdd

2.5V (+

5%), Vddq

2.5V (+

5%)

VVF: Vdd

1.8V (+

5%), Vddq

1.8V (+

5%)

• JEDEC 100-Pin QFP, 119-pin BGA, and 165-pin

BGA packages

• Lead-free available

MARCH 2020

DESCRIPTION

The 9Mb product family features high-speed, low-power

synchronous static RAMs designed to provide burstable,

high-performance memory for communication and network-

ing applications. The IS61(64)LF/VF25636B

is organized

as 262,144 words by 36 bits. The IS61(64)LF/VF51218B

is organized as 524,288 words by 18 bits. Fabricated with

ISSI

's advanced CMOS technology, the device integrates

a 2-bit burst counter, high-speed SRAM core, and high-

drive capability outputs into a single monolithic circuit. All

synchronous inputs pass through registers controlled by

a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be one to

four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be writ-

ten. Byte write operation is performed by using byte write

enable (BWE)

input combined with one or more individual

byte write signals (BWx). In addition, Global Write (GW)

is available for writing all bytes at one time, regardless of

the byte write controls.

Bursts can be initiated with either

ADSP

(Address Status

Processor) or

ADSC

(Address Status Cache Controller)

input pins. Subsequent burst addresses can be gener-

ated internally and controlled by the

ADV

(burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Inter-

leave burst is achieved when this pin is tied HIGH or left

floating.

FAST ACCESS TIME

Symbol

tkq

tkc

Parameter

Clock Access Time

Cycle Time

Frequency

-6.5

6.5

7.5

133

-7.5

7.5

8.5

117

Units

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause

failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written

assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. B2

03/04/2020