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NSBC123JPDXV6T1

产品描述trans prebias npn/pnp sot563
产品类别分立半导体    晶体管   
文件大小135KB,共14页
制造商ON Semiconductor(安森美)
官网地址http://www.onsemi.cn
标准
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NSBC123JPDXV6T1概述

trans prebias npn/pnp sot563

NSBC123JPDXV6T1规格参数

参数名称属性值
是否Rohs认证符合
厂商名称ON Semiconductor(安森美)
包装说明PLASTIC, CASE 463A-01, 6 PIN
针数6
制造商包装代码CASE 463A-01
Reach Compliance Codeunknown
ECCN代码EAR99
其他特性BUILT IN BIAS RESISTOR RATIO IS 21.36
最大集电极电流 (IC)0.1 A
集电极-发射极最大电压50 V
配置SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR
最小直流电流增益 (hFE)80
JESD-30 代码R-PDSO-F6
JESD-609代码e3
元件数量2
端子数量6
封装主体材料PLASTIC/EPOXY
封装形状RECTANGULAR
封装形式SMALL OUTLINE
峰值回流温度(摄氏度)260
极性/信道类型NPN AND PNP
最大功率耗散 (Abs)0.5 W
认证状态Not Qualified
表面贴装YES
端子面层Tin (Sn)
端子形式FLAT
端子位置DUAL
处于峰值回流温度下的最长时间40
晶体管应用SWITCHING
晶体管元件材料SILICON

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NSBC114EPDXV6T1,
NSBC114EPDXV6T5
Dual Bias Resistor
Transistors
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base-emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the NSBC114EPDXV6T1
series, two complementary BRT devices are housed in the SOT-563
package which is ideal for low power surface mount applications
where board space is at a premium.
Features
(3)
R
1
Q
1
Q
2
R
2
(4)
R
1
(5)
(6)
http://onsemi.com
(2)
R
2
(1)
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
Available in 8 mm, 7 inch Tape and Reel
Pb-Free Packages are Available
6
1
SOT-563
CASE 463A
PLASTIC
MAXIMUM RATINGS
(T
A
= 25°C unless otherwise noted, common for Q
1
and Q
2
, - minus sign for Q
1
(PNP) omitted)
Rating
Collector‐Base Voltage
Collector‐Emitter Voltage
Collector Current
Symbol
V
CBO
V
CEO
I
C
Value
50
50
100
Unit
Vdc
Vdc
mAdc
MARKING DIAGRAM
xx MG
G
xx = Specific Device Code
(see table on page 2)
M = Date Code
G
= Pb-Free Package
(Note: Microdot may be in either location)
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Total Device Dissipation
T
A
= 25°C (Note 1)
Derate above 25°C (Note 1)
Thermal Resistance (Note 1)
Junction‐to‐Ambient
Characteristic
(Both Junctions Heated)
Total Device Dissipation
T
A
= 25°C (Note 1)
Derate above 25°C (Note 1)
Thermal Resistance (Note 1)
Junction‐to‐Ambient
Junction and Storage Temperature
Symbol
P
D
357
2.9
R
qJA
350
Max
500
4.0
R
qJA
T
J
, T
stg
250
- 55 to +150
Unit
mW
mW/°C
°C/W
°C
mW
mW/°C
°C/W
Max
Unit
ORDERING INFORMATION
Device
Package
Shipping
4 mm pitch
4000/Tape & Reel
2 mm pitch
8000/Tape & Reel
NSBC114EPDXV6T1 SOT-563
NSBC114EPDXV6T5 SOT-563
Symbol
P
D
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR-4 @ Minimum Pad
DEVICE MARKING INFORMATION
See specific marking information in the device marking table
on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2008
1
January, 2008 - Rev. 4
Publication Order Number:
NSBC114EPDXV6/D

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