F384-Series Specifications
(MIL-PRF-38534)
Flat Pack
PDI Model F384 series is a high reliability product designed, processed and tested in our
Middleton facility and certified to MIL-PRF-38534H. This “flat pack” product with hybrid
assembly design and construction provides for superior long term reliability. Standard and
custom frequencies are available and make this product ideal for Aerospace, Military, Avionic,
Medical, and any other application requiring MIL-PRF-38534 certified content.
ex)
F384—T—25000X—M—C—D—3—X—X
*
* - for standard or assigned for customization.
ENABLE
T
= Tri-State
X
= No Connect
CMOS SPECIFICATIONS
FREQUENCY
00750X-99999X=
0.7500MHz -
99.999MHz
C10000-C80000=
100.00MHz -
800.00MHz
OUTPUT
M
= LVDS
O
= LVCMOS
P
= LVPECL
FREQUENCY
STABILITY
B
= ±25 **
C
= ±50
S
= Special
OPERATING
TEMPERATURE
B
= -20°C to +70°C
D
= -40°C to +85°C
E
= -55°C to +125°C
S
= Special
SUPPLY
VOLTAGE
2
= 2.5V
3
= 3.3V
LEAD FORM
G
= Gull Wing
X
= None
S
= Special
** - Not available -55 to +125°C
Param ete r
Frequency Range
Frequency Stability
*1
Temperature Range
*1
*1
S u pp l y Vol ta ge
*1
( ±1 0 % )
3 .3
2 .5
*2
Units
V
MHz
ppm
°C
°C
Supply Current (Maximum)
Output
Load
Duty Cycle (at 50% Vcc)
Rise/Fall Times (Maximum)
Start up Time (Maximum)
Output Voltage Levels
All Causes (Maximum )
Operating
Storage
0.030000 to 23.999999 MHz
24.000000 to 49.999999 MHz
50.000000 to 69.999999 MHz
70.000000 to 200.000000 MHz
0.750000 to 200.0000
Per Option
Per Option
-55 to +125
15
20
30
45
15
20
30
45
mA
Rise Time (10% to 90% Vcc)
Fall Time (90% to 10% Vcc)
High (Minimum)
Low (Maximum)
High (See below) or Open
Low (See below)
*3
High Value (Minimum)
Low Value (Maximum)
*3
Disable Current (Maximum)
*3
Enable Delay Time (Maximum)
Disable Delay Time (Maximum)
Pin 1 (Tri-State) (Option)
Per Option
15pF/10 TTL gates
40 to 60% (45 to 55% option)
8
7
8
7
10
90
10
Enable
Disable
80
80
20
20
10
10
10
150
ns
ms
% Vcc
% Vcc
% Vcc
uA
ms
ns
*1 - Not all Frequency/Temperature/Voltage combinations are available.
*2 - Inclusive of Tolerance @25°C, Operating Temperature, Supply Voltage, Load, Aging, Shock and Vibration.
*3 - Internal crystal oscillation halted.
REV:
NA
SIZE:
A
CAGE:
A
1
of
4
F384-Series Specifications
(MIL-PRF-38534)
LVDS SPECIFICATIONS
Pa ram ete r
Frequency Range
Frequency Stability
*1
Temperature Range
*1
Supply Current (Maximum)
Output
Load (Typical)
Duty Cycle (Maximum)
Rise/Fall Times (Maximum)
Start up Time (Maximum)
Output Voltage Levels
Differential Voltage
High (See below) or Open
Low (See below)
*3
High Value (Minimum)
Low Value (Maximum)
*3
Disable Current (Typical)
*3
Enable Delay Time (Maximum)
Disable Delay Time (Maximum)
12KHz to 20MHz
@ 10KHz Offset
@ 100KHz Offset
High Voh (RL = 100Ω)
Low Vol (RL = 100Ω)
*1
Supply Voltage
*1
(±5%)
3 .3
2.5
*2
Units
V
MHz
ppm
°C
°C
mA
Ω
%
nS
mS
V
mV
All Causes (Maximum )
Operating
Storage
Between Output and Comp Output
@ 50% Vcc
Rise Time (20% to 80% Vcc)
Fall Time (80% to 20% Vcc)
Pin 1 (Tri-State) (Option)
Integrated Phase Jitter (RMS)
Phase Noise (Typical)
24.000000 to 800.000000
Per Option
Per Option
-55 to +125
80
LVDS
100
45/55
0.4
0.4
10.0
1.43 Typical , 1.60 Maximum
0.90 Minimum , 1.10 Typical
250 Min , 350 Typ , 450 Max
Enable
Disable
70
30
10
2.0
0.2
0.3 Typical , 1.0 Maximum
-138
-144
% Vcc
% Vcc
uA
mS
uS
pS
dBc/Hz
LVPECL SPECIFICATIONS
Pa ram ete r
Frequency Range
*1
Frequency Stability
*1
Temperature Range
*1
Supply Current (Maximum)
Output
Load (Typical)
Duty Cycle (Maximum)
Rise/Fall Times (Maximum)
Start up Time (Maximum)
Output Voltage Levels
Differential Voltage
High (See below) or Open
Low (See below)
*3
High Value (Minimum)
Low Value (Maximum)
*3
Disable Current (Typical)
*3
Enable Delay Time (Maximum)
Disable Delay Time (Maximum)
12KHz to 20MHz
@ 10KHz Offset
@ 100KHz Offset
REV:
NA
Supply Voltage
*1
(±5%)
3.3
2 .5
*2
Units
V
MHz
ppm
°C
°C
mA
Ω
%
nS
mS
V
mV
All Causes (Maximum )
Operating
Storage
Into Vcc-2V
@ 50% Vcc
Rise Time (20% to 80% Vcc)
Fall Time (80% to 20% Vcc)
High Voh (50Ω to Vcc-2V)
Low Vol (50Ω to Vcc-2V)
Pin 1 (Tri-State) (Option)
Integrated Phase Jitter (RMS)
Phase Noise (Typical)
24.000000 to 800.000000
Per Option
Per Option
-55 to +125
100
LVPECL
50
45/55
0.5
0.5
10.0
Vcc-1.025 Min, Vcc-0.95 Typ, Vcc-0.88 Max
Vcc-1.810 Min, Vcc-1.70 Typ, Vcc-1.62 Max
595 Min , 750 Typ , 930 Max
Enable
Disable
70
30
10
2.0
0.2
0.2 Typical , 1.0 Maximum
-138
-144
SIZE:
A
CAGE:
A
% Vcc
% Vcc
uA
mS
uS
pS
dBc/Hz
2
of
4
F384-Series Specifications
(MIL-PRF-38534)
MIL -P RF - 3 85 34 H , C las s H D evic e Scree ning
Test or Inspection
Preseal Burn-In
Non-Destructive Bond Pull
Internal Visual
Temperature Cycling
Mechanical Shock or Constant
Acceleration
PIND
Pre-Burn-In Electrical Test
Burn-In
Final Electrical Test
Seal (Fine and Gross)
Radiographic
External Visual Screen
MIL-STD-883
Method
1030
2023
2017
1010
2002 or 2001
2020
IAW applicable device
specification
1015
IAW applicable device
specification
1014
2012
2009
C , 10 Cycles
B , (Y1 direction only)
3,000 G’s (Y1 direction
only)
Condition
Requirement
Optional
Optional
100%
100%
100%
Optional
Optional
100%
100%
100%
Optional
100%
Reference Paragraph
C.5.3
C.5.4
C.5.5
C.5.6
C.5.6
C.5.7
C.5.8
C.5.9
C.5.10
C.5.11
C.5.12
C.5.13
REV:
NA
SIZE:
A
CAGE:
A
3
of
4
F384-Series Specifications
(MIL-PRF-38534)
PA C K A G E D I M E N S I O N S
Tolerance: ±.008 [.20mm] (Unless otherwise specified)
PIN
1
2-6
7
9
10
11-13
14
CONNECTION
Tri-State or No Connect
No Connect
Ground/Case
Output
Comp. Out or No Connect
No Connect
Supply Voltage
ESD Symbol
For Pin 1
1
.800 ±.010
[20.32 ±.25]
Top View
14
.100 Typ
[2.54 Typ]
Frequency
PDI Part #
D/C
S/N
.600
[15.24]
.500
[12.70]
.800 ±.010
[20.32 ±.25]
9
.015 ±.003
[.38 ±.05]
7
.470 Min
[11.94 Min]
Traceability Code
.300 Max
[7.62 Max]
.160 ±.005
[4.06 ±.13]
.010 ±.002
[.25 ±.05]
.080 ±.010
[2.03 ±.25]
Gullwing Detail
.160 ±.004
[4.06 ±.10]
.000 - .003
[.00 - .08]
.140 ±.020
[3.56 ±.51]
REV:
NA
SIZE:
A
CAGE:
A
4
of
4
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
