Product Specification
ASD0400
Ultra Low Power Dual 20/40/65/80 MSPS, 10-bit Analog-to-Digital Converter
Features
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Description
The ASD0400 is a high performance low power dual
analog-to-digital converter (ADC). The ADC employs
internal reference circuitry, a CMOS control interface and
CMOS output data, and is based on a proprietary structure.
Digital error correction is employed to ensure no missing
codes in the complete full scale range.
Several idle modes with fast startup times exist. Each
channel can independently be powered down and the entire
chip can either be put in Standby Mode or Power Down
mode. The different modes are optimized to allow the user
to select the mode resulting in the smallest possible energy
consumption during idle mode and startup.
The ASD0400 has a highly linear THA optimized for
frequencies up to Nyquist. The differential clock interface
is optimized for low jitter clock sources and supports
LVDS, LVPECL, sine wave and CMOS clock inputs.
10-bit resolution
20/40/65/80 MSPS maximum sampling rate
Ultra-Low Power Dissipation: 24/43/65/78 mW
61.6 dB SNR at 8 MHz F
IN
Internal reference circuitry
1.8 V core supply voltage
1.7 – 3.6 V I/O supply voltage
Parallel CMOS output
64 pin QFN package
Dual channel
Pin compatible with ASD0500
Applications
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Medical Imaging
Portable Test Equipment
Digital Oscilloscopes
IF Communication
Functional Block Diagram
AVDD
AVSS
DVDDCK
DVSSCK
DVDD
DVSS
CM_EXTBC
SLP_N
PD_N
CM_EXT
Control Interface
CKN
CK_EXT
ORNG_0
D0
OE_N_0
ORNG_1
D1
OE_N_1
IP0
IN0
IP1
IN1
ADC
10
ADC
10
Figure 1: Functional Block Diagram
Vestre Rosten 81, 7075 Tiller, Norway
Phone: +47 73 10 29 00, Fax: +47 73 10 29 19
Page 1 of 16
CKP
CLK
Org. No: NO 991 265 163MVA
www.arcticsilicon.com
Confidential
Product Specification
Table of Contents
Features............................................................................1
Applications.....................................................................1
Description.......................................................................1
Functional Block Diagram...............................................1
Specifications...................................................................3
Digital and timing Specifications.....................................8
Timing Diagram...............................................................9
Absolute Maximum Ratings.............................................9
Pin Configuration and Description.................................10
Recommended Usage.....................................................11
Package Mechanical Data..............................................15
Product Information.......................................................16
Ordering information......................................................16
Datasheet status..............................................................16
ASD0400
rev v3.2, 2010.04.23
Page 2 of 16
Confidential
Product Specification
Specifications
AVDD=1.8V, DVDD=1.8V, DVDDCK=1.8V, OVDD=2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, unless
otherwise noted
Parameter
DC accuracy
No missing codes
Offset error
Gain error
Gain matching
DNL
INL
V
CM
Analog Input
Input common mode
Full scale range
Input capacitance
Bandwidth
Power Supply
Core Supply Voltage
I/O Supply Voltage
Condition
Min
Typ
Guaranteed
Max
Unit
Midscale offset
Full scale range deviation from typical
Gain matching between channels. +/- 3 sigma value at worst case
conditions
Differential nonlinearity
Integral nonlinearity
Common mode voltage output
1
+/- 6
+/- 0.5
+/- 0.15
+/- 0.2
V
AVDD
/2
LSB
%FS
%FS
LSB
LSB
V
Analog input common mode voltage
Differential input voltage range
Differential input capacitance
Input Bandwidth
V
CM
-0.1
2.0
2
500
V
CM
+0.2
V
Vpp
pF
MHz
Supply voltage to all 1.8V domain pins. See Pin Configuration and
Description
Output driver supply voltage (OVDD). Should be higher than or equal to
Core Supply Voltage (V
OVDD
≥ V
DVDD
)
1.7
1.7
1.8
2.5
2.0
3.6
V
V
ASD0400
rev v3.2, 2010.04.23
Page 3 of 16
Confidential
Product Specification
ASD0400L20
AVDD=1.8V, DVDD=1.8V, DVDDCK=1.8V, OVDD=2.5V, FS=20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, unless otherwise
noted.
Parameter
Performance
SNR
Signal to Noise Ratio
F
IN
= 2 MHz
F
IN
= 8 MHz
F
IN
≅
FS/2
F
IN
= 20 MHz
SNDR
Signal to Noise and Distortion Ratio
F
IN
= 2 MHz
F
IN
= 8 MHz
F
IN
≅
FS/2
F
IN
= 20 MHz
SFDR
Spurious Free Dynamic Range
F
IN
= 2 MHz
F
IN
= 8 MHz
F
IN
≅
FS/2
F
IN
= 20 MHz
HD2
Second order Harmonic Distortion
F
IN
= 2 MHz
F
IN
= 8 MHz
F
IN
≅
FS/2
F
IN
= 20 MHz
HD3
Third order Harmonic Distortion
F
IN
= 2 MHz
F
IN
= 8 MHz
F
IN
≅
FS/2
F
IN
= 20 MHz
ENOB
Effective number of Bits
F
IN
= 2 MHz
F
IN
= 8 MHz
F
IN
≅
FS/2
F
IN
= 20 MHz
Crosstalk
Power Supply
Analog supply current
Digital supply current
Output driver supply
Output driver supply
Analog power
Digital power
Total power Dissipation
Power Down
Sleep Mode 1
Sleep Mode 2
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
20
3
MSPS
MSPS
Power Dissipation, Sleep mode one channel
Power Dissipation, Sleep mode both channels
OVDD = 2.5V, 5pF load on output bits, F
IN
= 1 MHz, CK_EXT disabled
OVDD = 2.5V, 5pF load on output bits, F
IN
= 1 MHz, CK_EXT disabled
Digital core supply
2.5V output driver supply, sine wave input, F
IN
= 1 MHz, CK_EXT enabled
2.5V output driver supply, sine wave input, F
IN
= 1 MHz, CK_EXT disabled
8.2
1.7
2.8
2.3
14.8
8.8
23.6
9.9
15.2
7.7
mA
mA
mA
mA
mW
mW
mW
µW
mW
mW
Signal crosstalk between channels, F
IN1
=8MHz, F
IN0
=9.9MHz
9.7
10.0
9.9
9.8
9.9
-105
bits
bits
bits
bits
dB
-70
-80
-81
-70
-80
dBc
dBc
dBc
dBc
-80
-90
-90
-90
-90
dBc
dBc
dBc
dBc
70
80
81
70
80
dBc
dBc
dBc
dBc
60
61.7
61.6
60.5
61.6
dBFS
dBFS
dBFS
dBFS
60
61.7
61.6
61.6
61.6
dBFS
dBFS
dBFS
dBFS
Condition
Min
Typ
Max
Unit
ASD0400
rev v3.2, 2010.04.23
Page 4 of 16
Confidential
Product Specification
ASD0400L40
AVDD=1.8V, DVDD=1.8V, DVDDCK=1.8V, OVDD=2.5V, FS=40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, unless otherwise
noted.
Parameter
Performance
SNR
Signal to Noise Ratio
F
IN
= 2 MHz
F
IN
= 8 MHz
F
IN
≅
FS/2
F
IN
= 30 MHz
SNDR
Signal to Noise and Distortion Ratio
F
IN
= 2 MHz
F
IN
= 8 MHz
F
IN
≅
FS/2
F
IN
= 30 MHz
SFDR
Spurious Free Dynamic Range
F
IN
= 2 MHz
F
IN
= 8 MHz
F
IN
≅
FS/2
F
IN
= 30 MHz
HD2
Second order Harmonic Distortion
F
IN
= 2 MHz
F
IN
= 8 MHz
F
IN
≅
FS/2
F
IN
= 30 MHz
HD3
Third order Harmonic Distortion
F
IN
= 2 MHz
F
IN
= 8 MHz
F
IN
≅
FS/2
F
IN
= 30 MHz
ENOB
Effective number of Bits
F
IN
= 2 MHz
F
IN
= 8 MHz
F
IN
≅
FS/2
F
IN
= 30 MHz
Crosstalk
Power Supply
Analog supply current
Digital supply current
Output driver supply
Output driver supply
Analog power
Digital power
Total power Dissipation
Power Down
Sleep Mode 1
Sleep Mode 2
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
40
20
MSPS
MSPS
Power Dissipation, Sleep mode one channel
Power Dissipation, Sleep mode both channels
OVDD = 2.5V, 5pF load on output bits, F
IN
= 1 MHz, CK_EXT disabled
OVDD = 2.5V, 5pF load on output bits, F
IN
= 1 MHz, CK_EXT disabled
Digital core supply
2.5V output driver supply, sine wave input, F
IN
= 1 MHz, CK_EXT enabled
2.5V output driver supply, sine wave input, F
IN
= 1 MHz, CK_EXT disabled
14.4
3.4
5.1
4.2
25.9
16.6
42.5
9.7
25.7
11.3
mA
mA
mA
mA
mW
mW
mW
µW
mW
mW
Signal crosstalk between channels, F
IN1
=8MHz, F
IN0
=9.9MHz
9.7
9.9
9.9
9.9
9.9
-100
bits
bits
bits
bits
dB
-70
-80
-81
-72
-80
dBc
dBc
dBc
dBc
-80
-90
-90
-85
-85
dBc
dBc
dBc
dBc
70
80
81
72
80
dBc
dBc
dBc
dBc
60.0
61.6
61.6
61.2
61.4
dBFS
dBFS
dBFS
dBFS
60.0
61.6
61.6
61.6
61.5
dBFS
dBFS
dBFS
dBFS
Condition
Min
Typ
Max
Unit
ASD0400
rev v3.2, 2010.04.23
Page 5 of 16
Confidential
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