CAT24C01, CAT24C02,
CAT24C04, CAT24C08, CAT24C16
1-Kb, 2-Kb, 4-Kb, 8-Kb and 16-Kb CMOS Serial EEPROM
FEATURES
Supports Standard and Fast I²C protocol
1.7V to 5.5V Supply Voltage Range
16-Byte Page Write Buffer
Hardware Write Protection for entire memory
Schmitt Triggers and Noise Suppression Filters
on I²C Bus Inputs (SCL and SDA).
Low power CMOS technology
1,000,000 program/erase cycles
100 year data retention
Industrial and Extended temperature range
RoHS-compliant 8-lead PDIP, SOIC, MSOP
and TSSOP, 8-pad TDFN and 5-lead TSOT-23
packages.
For Ordering Information details, see page 16.
DEVICE DESCRIPTION
The CAT24C01/02/04/08/16 are 1-Kb, 2-Kb, 4-Kb,
8-Kb and 16-Kb respectively CMOS Serial EEPROM
devices organized internally as 8/16/32/64 and 128
pages respectively of 16 bytes each. All devices
support both the Standard (100kHz) as well as Fast
(400kHz) I²C protocol.
Data is written by providing a starting address, then
loading 1 to 16 contiguous bytes into a Page Write
Buffer, and then writing all data to non-volatile
memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data
serially while automatically incrementing the internal
address count.
External address pins make it possible to address
up to eight CAT24C01 or CAT24C02, four CAT24C04,
two CAT24C08 and one CAT24C16 device on the
same bus.
PIN CONFIGURATION
PDIP (L), SOIC (W),
TSSOP (Y), MSOP (Z),
TDFN (VP2)
CAT24C16 / 08 / 04 / 02 / 01
NC / NC / NC / A
0
/ A
0
NC / NC / A
1
/ A
1
/ A
1
NC / A
2
/ A
2
/ A
2
/ A
2
V
SS
1
2
3
4
8
7
6
5
V
CC
SCL
WP
SCL
SDA
SDA
FUNCTIONAL SYMBOL
V
CC
TSOT-23 (TD)
1
2
3
4
V
CC
A
2
, A
1
, A
0
WP
CAT24Cxx
SDA
5
WP
SCL
V
SS
For the location of Pin 1, please consult the
corresponding package drawing.
PIN FUNCTIONS
Name
A
0
, A
1
, A
2
SDA
SCL
WP
V
CC
V
SS
NC
Description
Device Address Input
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
Not Connect
*
V
SS
The Green & Gold seal identifies RoHS-compliant packaging,
using NiPdAu pre-plated lead frames.
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
1
Doc. No. MD-1115 Rev. G
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
ABSOLUTE MAXIMUM RATINGS
(1)
Storage Temperature
Voltage on any pin with respect to Ground
RELIABILITY CHARACTERISTICS
(3)
Symbol
N
END(4)
T
DR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/Erase Cycles
Years
(2)
-65°C to +150°C
-0.5V to +6.5V
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.8V to 5.5V, T
A
= -40°C to +125°C and V
CC
= 1.7V to 5.5V, T
A
= -40°C to +85°C, unless otherwise specified.
Symbol Parameter
I
CCR
I
CCW
I
SB
Read Current
Write Current
Standby Current
Test Conditions
Read, f
SCL
= 400kHz
Write, f
SCL
= 400kHz
All I/O Pins at GND or V
CC
T
A
= -40°C to +85°C
T
A
= -40°C to
I
L
V
IL
V
IH
V
OL1
V
OL2
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage V
CC
< 2.5V, I
OL
= 3.0mA
Output Low Voltage V
CC
< 2.5V, I
OL
= 1.0mA
Pin at GND or V
CC
T
A
= -40°C to +85°C
T
A
= -40°C to
-0.5
V
CC
x 0.7
Min
Max
1
2
1
2
1
2
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.2
V
V
V
V
µA
Units
mA
mA
µA
PIN IMPEDANCE CHARACTERISTICS
V
CC
= 1.8V to 5.5V, T
A
= -40°C to +125°C and V
CC
= 1.7V to 5.5V, T
A
= -40°C to +85°C, unless otherwise specified.
Symbol Parameter
C
IN
C
IN
(3)
(3)
Conditions
V
IN
= 0V
V
IN
= 0V
V
IN
< 0.5 x V
CC
, V
CC
= 5.5V
V
IN
< 0.5 x V
CC
, V
CC
= 3.3V
V
IN
< 0.5 x V
CC
, V
CC
= 1.8V
V
IN
> 0.5 x V
CC
Max
8
6
200
150
100
1
Units
pF
pF
SDA I/O Pin Capacitance
Input Capacitance (other pins)
I
WP
(5)
WP Input Current
µA
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than V
CC
+ 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than V
CC
+ 1.5V, for periods of less than 20ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, V
CC
= 5V, 25°C.
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull-down reverts to a weak current source.
Doc. No. MD-1115 Rev. G
2
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
A.C. CHARACTERISTICS
(1)
V
CC
= 1.8V to 5.5V, T
A
= -40°C to +125°C and V
CC
= 1.7V to 5.5V, T
A
= -40°C to +85°C, unless otherwise specified.
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F(2)
t
SU:STO
t
BUF
t
AA
t
DH
T
i(2)
t
SU:WP
t
HD:WP
t
WR
t
PU(2, 3)
Parameter
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power-up to Ready Mode
0
2.5
5
1
100
100
0
2.5
5
1
4
4.7
3.5
100
100
4
4.7
4
4.7
0
250
1000
300
0.6
1.3
0.9
Standard
Min
Max
100
0.6
1.3
0.6
0.6
0
100
300
300
Min
Fast
Max
400
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
ns
ns
µs
µs
ms
ms
Units
A.C. TEST CONDITIONS
Input Drive Levels
Input Rise and Fall Time
Input Reference Levels
Output Reference Level
Output Test Load
0.2 x V
CC
to 0.8 x V
CC
≤
50ns
0.3 x V
CC
, 0.7 x V
CC
0.5 x V
CC
Current Source I
OL
= 3mA (V
CC
≥
2.5V); I
OL
= 1mA (V
CC
< 2.5V); C
L
= 100pF
Notes:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
3
Doc. No. MD-1115 Rev. G
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
POWER-ON RESET (POR)
Each CAT24Cxx* incorporates Power-On Reset
(POR) circuitry which protects the internal logic
against powering up in the wrong state.
A CAT24Cxx device will power up into Standby mode
after V
CC
exceeds the POR trigger level and will power
down into Reset mode when V
CC
drops below the
POR trigger level. This bi-directional POR feature
protects the device against ‘brown-out’ failure
following a temporary loss of power.
* For common features, the CAT24C01/02/04/08/16 will be refered
to as CAT24Cxx
I²C BUS PROTOCOL
The I²C bus consists of two ‘wires’, SCL and SDA.
The two wires are connected to the V
CC
supply via
pull-up resistors. Master and Slave devices connect to
the 2-wire bus via their respective SCL and SDA pins.
The transmitting device pulls down the SDA line to
‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is high. An SDA transition while
SCL is high will be interpreted as a START or STOP
condition (Figure 1). The START condition precedes
all commands. It consists of a HIGH to LOW transition
on SDA while SCL is HIGH. The START acts as a
‘wake-up’ call to all receivers. Absent a START, a
Slave will not respond to commands. The STOP
condition completes all commands. It consists of a
LOW to HIGH transition on SDA while SCL is HIGH.
DEVICE ADDRESSING
The Master initiates data transfer by creating a
START condition on the bus. The Master then
broadcasts an 8-bit serial Slave address. For normal
Read/Write operations, the first 4 bits of the Slave
address are fixed at 1010 (Ah). The next 3 bits are
used as programmable address bits when cascading
multiple devices and/or as internal address bits. The
¯¯
last bit of the slave address, R/W , specifies whether a
Read (1) or Write (0) operation is to be performed.
The 3 address space extension bits are assigned as
illustrated in Figure 2. A
2
, A
1
and A
0
must match the
state of the external address pins, and a
10
, a
9
and a
8
are internal address bits.
ACKNOWLEDGE
After processing the Slave address, the Slave
responds with an acknowledge (ACK) by pulling down
the SDA line during the 9th clock cycle (Figure 3). The
Slave will also acknowledge the address byte and
every data byte presented in Write mode. In Read
mode the Slave shifts out a data byte, and then
releases the SDA line during the 9
th
clock cycle. As
long as the Master acknowledges the data, the Slave
will continue transmitting. The Master terminates the
session by not acknowledging the last data byte
(NoACK) and by issuing a STOP condition. Bus timing
is illustrated in Figure 4.
PIN DESCRIPTION
SCL:
The Serial Clock input pin accepts the Serial
Clock generated by the Master.
SDA:
The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode,
this pin is open drain. Data is acquired on the positive
edge, and is delivered on the negative edge of SCL.
A0, A1 and A2:
The Address inputs set the device
address when cascading multiple devices. When not
driven, these pins are pulled LOW internally.
WP:
The Write Protect input pin inhibits all write
operations, when pulled HIGH. When not driven, this
pin is pulled LOW internally.
FUNCTIONAL DESCRIPTION
The CAT24Cxx supports the Inter-Integrated Circuit
(I²C) Bus data transmission protocol, which defines a
device that sends data to the bus as a transmitter and
a device receiving data as a receiver. Data flow is
controlled by a Master device, which generates the
serial clock and all START and STOP conditions. The
CAT24Cxx acts as a Slave device. Master and Slave
alternate as either transmitter or receiver.
Doc. No. MD-1115 Rev. G
4
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
Figure 1. Start/Stop Timing
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Slave Address Bits
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
A2
A2
A2
a10
A1
A1
a9
a9
A0
a8
a8
a8
R/W
R/W
R/W
R/W
CAT24C01 and CAT24C02
CAT24C04
CAT24C08
CAT24C16
Figure 3. Acknowledge Timing
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
8
9
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ tSU:DAT)
START
ACK DELAY (≤ tAA)
Figure 4. Bus Timing
t
F
t
LOW
SCL
t
SU:STA
t
HD:SDA
SDA IN
t
AA
SDA OUT
t
DH
t
BUF
t
HD:DAT
t
SU:DAT
t
SU:STO
t
HIGH
t
LOW
t
R
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
5
Doc. No. MD-1115 Rev. G
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