SN54/74LS194A
4-BIT BIDIRECTIONAL
UNIVERSAL SHIFT REGISTER
The SN54 / 74LS194A is a High Speed 4-Bit Bidirectional Universal Shift
Register. As a high speed multifunctional sequential building block, it is useful
in a wide variety of applications. It may be used in serial-serial, shift left, shift
right, serial-parallel, parallel-serial, and parallel-parallel data register trans-
fers. The LS194A is similar in operation to the LS195A Universal Shift
Register, with added features of shift left without external connections and
hold (do nothing) modes of operation. It utilizes the Schottky diode clamped
process to achieve high speeds and is fully compatible with all Motorola TTL
families.
4-BIT BIDIRECTIONAL
UNIVERSAL SHIFT REGISTER
LOW POWER SCHOTTKY
•
•
•
•
•
Typical Shift Frequency of 36 MHz
Asynchronous Master Reset
Hold (Do Nothing) Mode
Fully Synchronous Serial or Parallel Data Transfers
Input Clamp Diodes Limit High Speed Termination Effects
J SUFFIX
CERAMIC
CASE 620-09
16
1
CONNECTION DIAGRAM DIP
(TOP VIEW)
VCC
16
Q0
15
Q1
14
Q2
13
Q3
12
CP
11
S1
10
S0
9
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
1
MR
2
DSR
3
P0
4
P1
5
P2
6
P3
7
8
DSL GND
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
PIN NAMES
LOADING
(Note a)
HIGH
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
S0, S1
P0 – P3
DSR
DSL
CP
MR
Q0 – Q3
Mode Control Inputs
Parallel Data Inputs
Serial (Shift Right) Data Input
Serial (Shift Left) Data Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Parallel Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40
µA
HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b.
Temperature Ranges.
FAST AND LS TTL DATA
5-1
SN54/74LS194A
LOGIC DIAGRAM
10
P0
3
P1
4
P2
5
P3
6
S1
9
S0
2
DSR
7
DSL
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
S
CP
Q0
S
CP
Q1
S
CP
Q2
S
CP
Q3
R
CLEAR
R
CLEAR
R
CLEAR
R
CLEAR
CP
MR
11
1
15
14
13
12
Q0
Q1
Q2
Q3
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the functional
Q3 outputs respectively following the next LOW to HIGH
characteristics of the LS194A 4-Bit Bidirectional Shift Regis-
transition of the clock.
ter. The LS194A is similar in operation to the Motorola LS195A
The asynchronous Master Reset (MR), when LOW, over-
rides all other input conditions and forces the Q outputs LOW.
Universal Shift Register when used in serial or parallel data
Special logic features of the LS194A design which increase
register transfers. Some of the common features of the two
the range of application are described below:
devices are described below:
Two mode control inputs (S0, S1) determine the synchro-
All data and mode control inputs are edge-triggered,
nous operation of the device. As shown in the Mode Selection
responding only to the LOW to HIGH transition of the Clock
Table, data can be entered and shifted from left to right (shift
(CP). The only timing restriction, therefore, is that the mode
right, Q0
→
Q1, etc.) or right to left (shift left, Q3
→
Q2, etc.), or
control and selected data inputs must be stable one set-up
parallel data can be entered loading all four bits of the register
time prior to the positive transition of the clock pulse.
simultaneously. When both S0 and S1,are LOW, the existing
The register is fully synchronous, with all operations taking
data is retained in a “do nothing” mode without restricting the
place in less than 15 ns (typical) making the device especially
HIGH to LOW clock transition.
useful for implementing very high speed CPUs, or the memory
D-type serial data inputs (DSR, DSL) are provided on both
buffer registers.
the first and last stages to allow multistage shift right or shift left
The four parallel data inputs (P0, P1, P2, P3) are D-type
data transfers without interfering with parallel load operation.
inputs. When both S0 and S1 are HIGH, the data appearing on
P0, P1, P2, and P3 inputs is transferred to the Q0, Q1, Q2, and
MODE SELECT — TRUTH TABLE
OPERATING MODE
Reset
Hold
Shift Left
Shift Right
Parallel Load
INPUTS
MR
L
H
H
H
H
H
H
S1
X
I
h
h
I
I
h
S0
X
I
I
I
h
h
h
DSR
X
X
X
X
I
h
X
DSL
X
X
I
h
X
X
X
Pn
X
X
X
X
X
X
Pn
Q0
L
q0
q1
q1
L
H
P0
Q1
L
q1
q2
q2
q0
q0
P1
OUTPUTS
Q2
L
q2
q3
q3
q1
q1
P2
Q3
L
q3
L
H
q2
q2
P3
L = LOW Voltage Level
H = HIGH Voltage Level
X = Don’t Care
I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition
h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition
pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition.
FAST AND LS TTL DATA
5-2
SN54/74LS194A
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Parameter
54
74
54
74
54, 74
54
74
Min
4.5
4.75
– 55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
– 0.4
4.0
8.0
Unit
V
°C
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
S b l
VIH
VIL
VIK
VOH
Parameter
P
Input HIGH Voltage
54
Input LOW Voltage
74
Input Clamp Diode Voltage
54
Output HIGH Voltage
74
54, 74
VOL
Output LOW Voltage
74
Input HIGH Current
0.1
Input LOW Current
Short Circuit Current (Note 1)
Power Supply Current
– 20
– 0.4
– 100
23
0.35
0.5
20
IIH
IIL
IOS
ICC
V
µA
mA
mA
mA
mA
2.7
3.5
0.25
0.4
V
V
2.5
– 0.65
3.5
0.8
– 1.5
V
V
Min
2.0
0.7
V
Typ
Max
Unit
U i
V
Test C di i
T
Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
p
g
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
,
,
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25°C)
Limits
Symbol
S b l
fMAX
tPLH
tPHL
tPHL
Parameter
P
Maximum Clock Frequency
Propagation Delay,
Clock to Output
Propagation Delay,
MR to Output
Min
25
Typ
36
14
17
19
22
26
30
Max
Unit
U i
MHz
ns
ns
VCC = 5.0 V
50
CL = 15 pF
Test C di i
T
Conditions
FAST AND LS TTL DATA
5-3
SN54/74LS194A
AC SETUP REQUIREMENTS
(TA = 25°C)
Limits
Symbol
S b l
tW
ts
ts
th
trec
Parameter
P
Clock or MR Pulse Width
Mode Control Setup Time
Data Setup Time
Hold time, Any Input
Recovery Time
Min
20
30
20
0
25
Typ
Max
Unit
U i
ns
ns
ns
ns
ns
VCC = 5.0 V
50
Test C di i
T
Conditions
DEFINITIONS OF TERMS
SETUP TIME(ts) —is defined as the minimum time required
for the correct logic level to be present at the logic input prior
to the clock transition from LOW to HIGH in order to be
recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW to HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and transfer
HIGH Data to the Q outputs.
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fmax
1.3 V
CLOCK
tPHL
OUTPUT
1.3 V
tW
tPLH
1.3 V
DSR DSL
ts(L)
th(L) = 0
P0 P1 P2 P3
ts(L)
th(L) = 0
CLOCK
OUTPUT*
MR
1.3 V
ts(H)
th(H) = 0
1.3 V
1.3 V
ts(H)
th(H) = 0
1.3 V
S1
S0
(––– IS SHIFT LEFT)
OTHER CONDITIONS: S1 = L, MR = H, S0 = H
Figure 1. Clock to Output Delays Clock Pulse
Width and fmax
1.3 V
tW
trec
1.3 V
OTHER CONDITIONS: MR = H
OTHER CONDITIONS:
*DSR SET-UP TIME AFFECTS Q0 ONLY
OTHER CONDITIONS:
DSL SET-UP TIME AFFECTS Q3 ONLY
CLOCK
tPHL
OUTPUT
1.3 V
Figure 3. Setup (ts) and Hold (th) Time for Serial Data
(DSR, DSL) and Parallel Data (P0, P1, P2, P3)
(STABLE TIME)
S0 S1
ts
th = 0
CLOCK
1.3 V
OTHER CONDITIONS: MR = H
ts
th = 0
1.3 V
1.3 V
OTHER CONDITIONS: S0, S1 = H
OTHER CONDITIONS:
PO = P1 = P2 = P3 = H
Figure 2. Master Reset Pulse Width, Master Reset
to Output Delay and Master Reset to Clock
Recovery Time
Figure 4. Setup (ts) and Hold (th) Time for S Input
FAST AND LS TTL DATA
5-4
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