D a ta s h e e t
AS1372
350mA Dual Rail Linear Regulator
1 General Description
The AS1372 is a Dual Supply Rail Linear Regulator
designed for providing ultra-low voltages.
In a typical application the battery is directly connected
to V
BIAS
and V
IN
is connected to the output of a DC-DC
Converter.
The very low quiescent currents together with the
excellent transient features and the superior dropout are
making the AS1372 an ideal device for applications
running on batteries.
The robust design ensures that no under-voltage failure
can occur and the device is also equipped with an
internal protection against over-temperature and over-
current.
The device is available in fixed output voltages from
0.5V up to 2.2V in 100mV steps (50mV from 0.5V to
1.1V).
The AS1372 is available in a 5-bumps CS-WLP package
and is qualified for -40°C to +85°C operation.
2 Key Features
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
Input Voltage: 0.7V to 4.5V
Bias Supply Voltage: 2.5V to 5.5V
Output Voltage: 0.5V to 2.2V in 100mV steps
Output Voltage Accuracy: ±1.5%
Dropout Voltage 135mV @ 350mA load
Max. Output Current: 350mA
Load Transient Response: ±15mV (typ.)
Superior Efficiency
Low Shutdown Current: 10nA
High PSRR: >80dB @ 10Hz-1kHz, 60db @100kHz
Noise Voltage: 50µV
RMS
from 10Hz to 1000kHz
Integrated Overtemperature/Overcurrent Protection
Chip Enable Input
Operating Temperature Range: -40°C to +85°C
5-bumps CS-WLP Package
3 Applications
The devices are ideal for powering cordless and mobile
phones, MP3 players, PDAs, hand-held computers,
digital cameras, and any other hand-held and/or battery-
powered device.
Figure 1. AS1372 - Typical Application Diagram
!
"#
$
www.austriamicrosystems.com/LDOs/AS1372
Revision 1.01
1 - 14
AS1372
Datasheet - P i n A s s i g n m e n t s
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
1
3
2
5
4
Pin Descriptions
Table 1. Pin Descriptions
Pin Number
1
2
3
4
5
Pin Name
VOUT
GND
EN
VBIAS
VIN
Description
Regulated Output Voltage.
Bypass this pin with a capacitor to GND.
Ground.
Enable.
Pull this pin to low to disable the device. This pin has an internal 1.6MΩ (typ.)
pull-down resistor.
Bias Supply Voltage.
2.5V to 5.5V, Bypass this pin with a capacitor to GND.
Unregulated Input Voltage.
0.7V to 4.5V, V
IN
≤
V
BIAS
, Bypass this pin with a
capacitor to GND.
www.austriamicrosystems.com/LDOs/AS1372
Revision 1.01
2 - 14
AS1372
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in
Table 2
may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in
Section 6 Electrical
Characteristics on page 4
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
VIN, VBIAS and EN to GND
VOUT to GND
Output Short-Circuit Duration
ESD
Latch-Up
Operating Temperature Range
Storage Temperature Range
Junction Temperature
-100
-40
-65
2
+100
+85
+150
+125
Min
-0.3
-0.3
Max
+6.5
V
IN
+ 0.3
Indefinite
kV
mA
ºC
ºC
ºC
The reflow peak soldering temperature
(body temperature) specified is in
accordance with
IPC/JEDEC J-STD-
020D “Moisture/Reflow Sensitivity
Classification for Non-Hermetic Solid
State Surface Mount Devices”.
The lead finish for Pb-free leaded
packages is matte tin (100% Sn).
HBM MIL-Std. 883E 3015.7
methods
JEDEC 78
Units
V
V
Notes
VIN < VBIAS or equal in operating
conditions
Package Body Temperature
+260
ºC
www.austriamicrosystems.com/LDOs/AS1372
Revision 1.01
3 - 14
AS1372
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
V
IN
= V
OUT
+ 0.2V, V
BIAS
= V
OUT
+ 1.5V (or 2.5V whichever is larger), EN = V
BIAS
, C
IN
= C
OUT
= C
BIAS
= 1µF, T
AMB
= -
40°C to +85ºC, Typical Values are at T
AMB
= +25ºC (unless otherwise specified).
Table 3. Electrical Characteristics
Symbol
V
IN
V
BIAS
V
OUT
Parameter
Input Voltage
Bias Supply Voltage
Output Voltage
Available in 50mV or 100mV steps
(see Ordering Information on page
13)
I
OUT
= 100µA
Output Voltage Accuracy
V
OUT
> 1.2V
V
OUT(NOM)
- V
OUT
Output Voltage Accuracy
V
OUT
≤
1.2V
ΔV
OUT
/
ΔV
IN
ΔV
OUT
/
ΔV
BIAS
ΔV
LDR
I
OUT
I
LIM
V
DROP
-
V
IN
I
OUT
= 100µA to 350mA, V
IN
=
V
OUT(NOM)
+0.2V to 4.5V, V
BIAS
=
V
OUT(NOM)
+1.5V to 5.5V
I
OUT
= 100µA
I
OUT
= 100µA to 350mA, V
IN
=
V
OUT(NOM)
+0.2V to 4.5V, V
BIAS
=
V
OUT(NOM)
+1.5V to 5.5V
V
IN
= V
OUT(NOM)
+0.2V to 4.5V,
V
BIAS
= 5.5V, I
OUT
= 100µA
V
BIAS
= V
OUT(NOM)
+1.5V to 5.5V,
I
OUT
= 100µA
I
OUT
= 1mA to 350mA
350
500
V
BIAS
= V
OUT
+ 1.5V, I
OUT
= 350mA
Output Voltage Dropout V
IN
V
BIAS
= V
OUT
+ 1.8V, I
OUT
= 350mA
V
BIAS
= 5.5V, I
OUT
= 350mA
V
DROP
-
V
BIAS
E
N
Output Voltage Dropout V
BIAS
Output Voltage Noise
I
OUT
= 100mA
V
OUT
≤
1.2V, f = 10Hz to 100kHz
f = 100Hz
PSRR -
V
IN
Power-Supply Rejection Ratio
Sine modulated V
IN
f = 1kHz
f = 10kHz
f = 100kHz
f = 100Hz
PSRR -
V
BIAS
Power-Supply Rejection
Ratio Sine modulated V
BIAS
f = 1kHz
f = 10kHz
f = 100kHz
I
Q_VBIAS
I
Q_VIN
Quiescent Current into V
BIAS
Quiescent Current into V
IN
I
OUT
= 0mA
135
115
110
1.1
50
85
80
70
60
75
60
50
50
40
6.5
75
10
µA
dB
dB
1.5
V
µV
RMS
mV
Conditions
V
IN
≤
V
BIAS
Min
0.7
2.5
0.5
-1.5
-2
-2
-2.5
40
100
6
Typ
Max
4.5
5.5
2.2
+1.5
+2
+2
+2.5
%
%
Units
V
V
V
Line Regulation V
IN
Line Regulation V
BIAS
Load Regulation
Output Current
Current Limit
1
µV/V
µV/V
µV/mA
mA
mA
www.austriamicrosystems.com/LDOs/AS1372
Revision 1.01
4 - 14
AS1372
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 3. Electrical Characteristics
Symbol
I
SHDN
-
V
BIAS
I
SHDN
-
V
IN
Logic Levels
V
IH
V
IL
I
EN
Enable Input Threshold
Enable Input Bias Current
EN = GND
1
0.4
0.01
V
nA
Parameter
Shutdown Current into V
BIAS
V
EN
= 0V
Shutdown Current into V
IN
10
Conditions
Min
Typ
10
nA
Max
Units
Thermal Protection
T
SHDN
ΔT
SHDN
Thermal Shutdown
Temperature
Thermal Shutdown Hysteresis
150
25
ºC
ºC
Transient Characteristics
ΔV
OUT
t
ON
C
OUT
Dynamic Load Transient
Response
Exit Delay from Shutdown
Output Capacitor
Pulsed I
LOAD
from 0mA to 300mA in
10µs rise time
V
OUT
≤
1.2V, setting to 95%
Load Capacitor Range
Maximum ESR Load
1. guaranteed by design
1
1
15
70
10
500
mV
µs
µF
mΩ
Note:
All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or
SQC (Statistical Quality Control) methods.
www.austriamicrosystems.com/LDOs/AS1372
Revision 1.01
5 - 14
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
