CA80C85B
HIGH PERFORMANCE 8-BIT
CMOS MICROPROCESSOR
• Enhanced, high performance CA80C85B
microprocessor features pin and functional
compatibility with industry standard 8085 and
8085A
• Very low power consumption achieved with
proven CMOS implementation
• TTL compatible input/output voltages
• Fast - Available in 8 MHz, 6 MHz, 5 MHz and 3
MHz speed versions
• Full support of extended instruction set, and
standard 8080 and 8085/8085A instruction sets
• Runs over 10,000 CP/M
®
programs
• On-chip clock generator (using external crystal,
LC or RC network)
• Direct addressing to 64K bytes
• Four Interrupt inputs (one non-maskable)
• One of the multi-sourced, Calmos™ 8000 series
products
The CA80C85B is an 8-bit microprocessor having complete
pin and functional compatibility with industry standard
8085s and 8085As. In addition, it supports the special 8085
extended instruction set. The CA80C85B includes an on-
board system controller, clock generator, serial I/O port and
direct addressing capability to 64K bytes of memory. The
device also utilizes a multiplexed data bus, with 16-bit
addresses split between an 8-bit address bus and an 8-bit
data bus.
The CA80C85B is manufactured in CMOS and supplied in a
PDIP package configuration suitable for commercial and
industrial applications.
The CA80C85B provides the systems designer with single
component CPU functionality, thereby reducing the parts
count. Its low power consumption and TTL I/O compatibil-
ity make the CA80C85B particularly well suited to portable
or standby type applications.
2
2.1
8000 Series Products
CA80C85B
CLK (OUT)
41
SOD
AD
4
V
SS
AD
5
AD
6
AD
7
X
1
X
2
RO
SOD
SID
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
INTA
AD
0
AD
1
AD
2
AD
3
AD
4
AD
5
AD
6
AD
7
V
SS
A
11
Figure 2-1: PDIP Pin Configurations
Figure 2-2: PLCC Pin Configurations
Tundra Semiconductor Corporation
A
10
A
12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
DD
HOLD
HLDA
CLK (OUT)
RESET IN
READY
IO / M
S
1
RD
WR
ALE
S
0
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
SID
RO
6
5
4
3
X
2
2
1
44
43
42
TRAP
RST 7.5
RST
6.5
RST 5.5
INTR
NC
INTA
AD
0
AD
1
AD
2
AD
3
40
RESET IN
HOLD
HLDA
VDD
NC
X
1
7
8
9
10
11
12
13
14
15
16
17
39
38
37
READY
IO/M
S
1
RD
WR
NC
ALE
S
0
A
15
A
14
A
13
18
19
20
21
22
23
24
25
26
27
A
8
A
9
28
CA80C85B
CA80C85B
44 - LEAD PLCC
36
35
34
33
32
31
30
29
2-1
CA80C85B
Tundra Semiconductor Corporation
INTR
INTA
RST6.5
TRAP
RST5.5
RST7.5
SID
SOD
INTERRUPT CONTROL
SERIAL I/O CONTROL
ACCUMULATORS
(8)
TEMPORARY
REGISTERS
(8)
FLAG
FLIPFLOPS
(5)
INSTRUCTION
REGISTERS
(8)
B REG
(8)
C REG
(8)
D REG
(8)
ARITHMETIC
LOGIC
UNIT
(ALU)
(8)
E REG
(8)
INSTRUCTION
DECODER
AND MACHINE
CYCLE
ENCODING
H REG
(8)
L REG
(8)
REGISTER
ARRAY
SP: STACK POINTER
(16)
PC: PROGRAM COUNTER
(16)
POWER
SUPPLY
+5V (VDD)
GND (VSS)
INCREMENTER / DECREMENTER
ADDRESS LATCH
(16)
X1
CLK
TIMING
AND
CONTROL
X2
GEN
CONTROL
CLK OUT
RD WR
READY
STATUS
ALE S0 S1 IO/M
DMA
HLDA
HOLD
RESET
RESET
OUT
RESET IN
ADDRESS BUFFER
(8)
DATA/ADDRESS
BUFFER
(8)
A15 - A8
ADDRESS BUS
AD7 - AD0
ADDRESS/DATA BUS
Figure 2-3: CA80C85B Block Diagram
2-2
Tundra Semiconductor Corporation
Tundra Semiconductor Corporation
CA80C85B
Table 2-1: Pin Descriptions
Symbol
PDIP
A
8
- A
15
AD
0
- AD
7
ALE
CLK
HLDA
Pin
21 - 28
12 - 19
30
37
38
Type
O
I/O
O
O
O
Name and Function
High Address Bus:
the most significant 8 bits of the memory address.
Low Address and Data Bus:
the least significant 8 bits of the memory address multiplexed with
an 8-bit data bus.
Address Latch Enable Out:
This signal occurs during the first clock state of a machine cycle.
The falling edge of the ALE may be used to strobe the status information.
Clock:
This signal can be used as a system clock. The period of CLK is twice the period of the
X
1
, X
2
input.
Hold Acknowledge:
Indicates that the CPU has received the HOLD request and that the bus will
be relinquished in the next clock cycle.
Hold Request:
Is used to indicate that another master is requesting the use of the address and
data buses. When HOLD is acknowledged (HLDA), the Address, Data,
RD
,
WR
and IO/
M
lines
are set to the high impedance state. Note that the CPU can regain control of the bus only after the
HOLD is removed.
Interrupt Acknowledge:
This active low signal indicates that the interrupt request input (INTR)
has been recognized and acknowledged.
Interrupt Request:
This is a general purpose interrupt. When INTR goes HIGH, it will inhibit
the Program Counter, generate an interrupt acknowledge (
INTA
) signal, and sample the data bus
for a RESTART or CALL instruction.
Machine Cycle Status:
See S
0
and S
1
status bits for further details.
Read Control:
Active low signal is used to indicate that selected memory or I/O device is to be
read with the data bus available for the data transfer.
RD
is set to a high impedance state during
HOLD, HALT and RESET modes.
Ready:
This signal is set to HIGH during read or write cycles to indicate that the selected
memory or I/O device is ready to send or receive data.
Reset In:
Active low signal sets the Program Counter to zero, and resets the interrupt enable
(INTE) and HLDA flipflop. Note that so long as
RESET IN
is held low, the CPU is held in a reset
condition.
Reset Out:
Indicates that the CPU is being reset. This signal can be used as a system RESET.
Restart Interrupts:
These inputs provide three maskable interrupts which invoke an automatic
internal restart. RST7.5 is the highest relative priority, followed by RST6.5 and RST5.5. All
three interrupts have a higher priority than INTR.
Status Outputs:
These signals provide an indication of the machine status during any given
cycle. All become valid at the beginning of a machine cycle, and remain stable for the duration of
that cycle. The status may be latched by the falling edge of the ALE signal.
Serial Input Data:
Data on SID is loaded into accumulator bit 7 when a RIM instruction is
executed.
Serial Output Data:
This signal is set or reset by the SIM instruction.
Trap Interrupt:
Is a non-maskable restart interrupt. It is the highest priority interrupt, and is
unaffected by an interrupt enable (INTE).
Power:
+5V supply
Ground:
Ground reference.
Write Control:
This active low signal is used to indicate that selected memory or I/O device is
to be written to, with the data bus available for the data transfer. WR is set to a high impedance
state during HOLD, HALT, and RESET modes.
X
1
, X
2
: These two inputs are connected to clock source which is used to drive the internal clock
generator. The clock source may be a crystal, LC or RC network. An external clock cal also be
connected directly to X
1
, to produce an internal processor clock frequency of one half of the
input frequency.
HOLD
39
I
INTA
11
10
34
32
35
36
3
7, 8, 9
O
O
O
O
I
I
O
I
INTR
IO/
M
RD
READY
RESET IN
RO
RST7.5
RST6.5
RST5.5
S
0
- S
1
IO/
M
SID
SOD
TRAP
V
DD
V
SS
WR
29, 33, 34
5
4
6
40
20
31
O
I
O
I
–
–
O
X
1
, X
2
1,2
I
Tundra Semiconductor Corporation
2-3
CA80C85B
Tundra Semiconductor Corporation
FUNCTIONAL DESIGN
The CA80C85B utilizes a stack architecture to enable any
part of the external memory to be employed as a Last In/First
Out (LIFO) memory stack. A 16-bit stack pointer controls
the addressing of this stack. The arrangement allows exten-
sive subroutine nesting and multiple level interrupts to be
handled without losing the system status. In addition, the
device accepts serial input data and provides serial output
data, functions which are controlled by the interrupt mask
instructions.
The CA80C85B provides 16-bit arithmetic operation with
immediate operators and decimal capability. An 8-bit accu-
mulator, four user accessible flag bits, an 8-bit parallel
binary arithmetic unit and six 8-bit data registers, all shown
in the block diagram of Figure 2-3, are also provided.
CA80C85B timing signals are supplied by an internal clock
generator (which can be used with either crystal or RC tim-
ing circuits), or by an external clock input signal. Status out-
puts convey memory I/O instruction and Read/Write timing
indications.
For typical, single function type configurations, the
CA80C85B is supplied in a 40-pin package, the low pin
count a result of multiplexing the Address and Data Bus
lines. Pin functions are described in Table 2-1, with the 40-
pin DIP pin configuration illustrated in Figure 2-1. The
lower processor pin count of this device can be reflected
throughout a system design by similar pin count reductions
in peripheral chips. Further, this optimization can be
achieved without incurring complex or critical timing prob-
lems.
The CA80C85B has five levels of interrupts, including three
maskable restart interrupts, one non-maskable TRAP inter-
rupt and a bus vectored interrupt, INTR. Bus control is pro-
vided by the
RD
,
WR
, S
0
, S
1
, IO/
M
and
INTA
interrupt
acknowledge signals. When a HOLD control input signal is
received, both Address and Data Bus are set to a high-imped-
ance state, and an HLDA output signal acknowledges that
microprocessor operation is stopped, and that the buses are
available for use by other devices. Note that HOLD and all
other interrupt signals are synchronized with the processor's
internal clock. This is illustrated in the processor state transi-
tion diagram of Figure 2-4.
In addition to the Data Bus, a simple serial interface is pro-
vided by the Serial Input Data (SID) and Serial Output Data
(SOD) lines.
At the software level, the CA80C85B supports the full
extended instruction set, offering 10 additional instructions
for the production of more efficient code. The five existing
condition code flags have also been enhanced with two addi-
tional flag bits, one of which indicates a 2s complement
overflow.
RESET
T
RESET
RESET
T
1
HALT
HALT
READY
1
T
2
(READY + B1)
T
WAIT
1
HOLD
VALIDINT
(READY + B1)
T
HALT
NO
HOLD = 1
YES
SET
HLDA FF
SET
HLDA FF
RESET
HALT FF
SET
INTA FF
2
HOLD = 1
2
NO
T
3
M1
T
4
CK = 6
YES
RESET
INTE FF
CK = 4
SET
HLDA FF
T
6
T
5
HLDA FF
= SET
NO
YES
HOLD
NO
LAST
MACHINE
CYCLE
YES
T
HOLD
HOLD
RESET
HLDA FF
NO
VALIDINT = 1
YES
SET
INTA FF
RESET
INTE FF
HALT = 1
NO
YES
Notes:
1.
BI
indicates that the bus is idle during this machine
cycle, though the processor itself is active
2.
CK
indicates the number of clock cycles in this
machine cycle.
Figure 2-4: State Transition Diagram
2-4
Tundra Semiconductor Corporation
Tundra Semiconductor Corporation
CA80C85B
Table 2-2: 3 MHz AC Characteristics
T
A
= –40° to +85°C, V
DD
= +5v + 10%, t
CYC
= 320 ns, C
L
= 150 pF
Limits
Symbol
t
1
t
2
t
AC
t
ACL
t
AD
t
AFR
t
AL
t
ALL
t
ARY
t
CA
t
CC
t
CL
t
CYC
t
DW
t
f
t
HABE
t
HABF
t
HACK
t
HDH
t
HDS
t
INH
t
INS
t
LA
t
LC
t
LCK
t
LDR
t
LDW
t
LL
t
LRY
t
r
t
RAE
t
RD
t
RDH
t
RV
t
RYH
t
RYS
t
WD
t
WDL
t
XKF
t
XKR
Parameter
Min
CLK Low Time
CLK High Time
A
8
- A
15
Valid to Leading Edge of Control (Note 1)
A
0
- A
7
Valid to Leading Edge of Control
A0 - A15 Valid to Valid Data In
Address Float After Leading Edge of
RD
,
INTA
A
8
- A
15
Valid Before Trailing Edge of ALE (Note 1)
A
0
- A
7
Valid Before Trailing Edge of ALE
READY Valid from Address Valid
Address (A
8
- A
15
) Valid After Control
Width of Control Low (
RD
,
WR
,
INTA
)
Trailing Edge of Control to Leading Edge of ALE
CLK Cycle Period
Data Valid to Trailing Edge of
WR
CLK Fall Time
HLDA to Bus Enable
Bus Float After HLDA
HLDA Valid to Trailing Edge of CLK
HOLD Hold Time
HOLD Setup Time to Trailing Edge of CLK
INTR Hold Time
INTR RST and TRAP Setup Time to Falling Edge of CLK
Address Hold Time After ALE
Trailing Edge of ALE to Leading Edge of Control
ALE Low During CLK High
ALE to Valid Data During Read
ALE to Valid Data During Write
ALE Width
ALE to Ready Stable
CLK Rise Time
Trailing Edge of RD to re-Enabling of Address
RD
(or
INTA
) to Valid Data
Data Hold Time After
RD
,
INTA
Control Trailing Edge to Leading Edge of Next Control
READY Hold Time
READY Setup Time to Leading Edge of CLK
Data Valid After Trailing Edge of
WR
Leading Edge of
WR
to Data Valid
X
1
Rising to CLK Falling
X
1
Rising to CLK Rising
80
120
270
240
-
-
115
90
-
120
400
50
320
420
-
-
-
110
0
170
0
160
100
130
100
-
-
140
-
-
150
-
0
400
0
110
100
-
20
20
Max
-
-
-
-
575
0
-
-
220
-
-
-
2000
-
30
210
210
-
-
-
-
-
-
-
-
460
200
-
110
30
-
300
-
-
-
-
-
40
150
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
Note: 1. A
8
- A
15
Address Specs apply to IO/
M
, S0 and S1. Except A
8
- A
15
are undefined during T
4
- T
6
of cycle whereas IO/
M
, S
0
and S
1
are stable.
Tundra Semiconductor Corporation
2-5
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