frequencies for a wide variety of applications. The
ICS843034-06 has a 4:1 input Multiplexer from
which the following inputs can be selected: one
differential input, one single-ended input, or two
crystal oscillators, thus making the device ideal for frequency
translation or frequency generation. The ICS843034-06 has
dual LVPECL outputs that may be programmed for ÷2, ÷4 or
÷5 from the VCO frequency. The ICS843034-06 also supplies
a buffered copy of the reference clock or crystal frequency on
the single-ended REF_OUT pin which can be enabled or
disabled (disabled by default). The output frequency can be
programmed using either a serial or parallel programming
interface. This device supports Spread Spectrum Clocking
(SSC) for EMI reduction.
F
EATURES
•
Dual differential 3.3V LVPECL outputs
•
4:1 Input Mux:
One differential input
One single-ended input
Two crystal oscillator interfaces
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•
REF_CLK accepts LVCMOS or LVTTL input levels
•
Output frequency range: 35MHz to 750MHz
•
Crystal input frequency range: 12MHz to 40MHz
•
VCO range: 560MHz to 750MHz
•
Supports Spread Spectrum Clocking (SSC)
•
Parallel or serial interface for programming feedback divider
and output dividers
•
RMS phase jitter at 333.33MHz, using a 22.222MHz crystal
(12kHz to 20MHz): 1.37ps (typical), SSC - Off
•
3.3V supply mode
•
0°C to 70°C ambient operating temperature
•
Industrial temperature available upon request
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
001
÷
2
011
÷
4
100
÷
5
IC
S
B
LOCK
D
IAGRAM
OE_A
Pullup
VCO_SEL
Pullup
XTAL_IN0
OSC
XTAL_OUT0
XTAL_IN1
XTAL_OUT1
OSC
01
00
0
FOUTA0
nFOUTA0
V
CCO_A
V
CCO_B
FOUTB0
nFOUTB0
M8
RESERVED
RESERVED
RESERVED
OE_REF
V
CCO_REF
OE_A
REF_OUT
OE_B
V
CC
NA0
TEST
NA1
NA2
V
EE
P
IN
A
SSIGNMENT
CLK
nCLK
nP_LOAD
VCO_SEL
M0
M1
M2
M3
M4
M5
M6
M7
CLK
Pullup
nCLK
Pullup/Pulldown
REF_CLK
Pulldown
SEL1
Pulldown
SEL0
Pulldown
OE_B
Pullup
MR
Pulldown
OE_REF
Pulldown
S_LOAD
Pulldown
S_DATA
Pulldown
S_CLOCK
Pulldown
nP_LOAD
Pulldown
10
11
Phase
VCO
Detector
÷
M
1
M8:M0
M0:M4 M6:M8 Pulldown, M5 Pullup
NA2:NA0
NA2 Pulldown, NA1:0 Pullup
Configuration
Interface
Logic
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
48-Pin LQFP
6
31
7mm x 7mm x 1.4mm
7
30
package body
8
29
Y Package
9
28
Top View
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
ICS843034-06
XTAL_OUT1
XTAL_IN1
XTAL_OUT0
XTAL_IN0
REF_CLK
SEL1
SEL0
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
V
EE
nc
V
CCO
_
REF
REF_OUT
V
CCO
_
B
nFOUTB0
FOUTB0
V
CCO
_
A
nFOUTA0
FOUTA0
V
CC
TEST
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
1
ICS843034AY-06 REV. A MARCH 7, 2007
ICS843034-06
FEMTOCLOCKS™ MULTI-RATE 3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes opera-
tion using a 25MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input
Frequency Characteristics, Table 5, NOTE 1.
The ICS843034-06 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a range
of 560MHz to 750MHz. The output of the M divider is also
applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the
LVPECL output buffers. The divider provides a 50% output duty
cycle.
The ICS843034-06 supports either serial or parallel programming
modes to program the M feedback divider and N output divider.
Figure 1
shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on the M and
NA inputs are passed directly to the M divider and N output divid-
ers. On the LOW-to-HIGH transition of the nP_LOAD input, the
data is latched and the M and N dividers remain loaded until the
next LOW transition on nP_LOAD or until a serial event occurs.
As a result, the M and NA bits can be hardwired to set the M
divider and NA output divider to a specific default state that will
automatically occur during power-up. The TEST output is LOW
when operating in the parallel input mode. The relationship
between the VCO frequency, the crystal frequency and the M
divider is defined as follows:
fVCO = fxtal x M
The M value and the required values of M0 through M8 are shown
in Table 4B to program the VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock for a 25MHz refer-
ence are defined as 23
≤
M
≤
30. The frequency out is defined as
follows:
FOUT = fVCO = fxtal x M
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider and NA output divider
when S_LOAD transitions from LOW-to-HIGH. The M divide
and NA output divide values are latched on the HIGH-to-LOW
transition of S_LOAD. If S_LOAD is held HIGH, data at the
S_DATA input is passed directly to the M divider and NA output
divider on each rising edge of S_CLOCK. The serial mode can
be used to program the M and NA bits and test bits T1 and T0.
The internal registers T0 and T1 determine the state of the
TEST output as follows:
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_Data, Shift Register Output
Output of M divider
FOUTA0 same frequency
S
ERIAL
L
OADING
S_CLOCK
S_DATA
S_LOAD
SSC3 SSC2 SSC1 SSC0
T1
T0
NU
NU
NU
NA2 NA1 NA0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S
t
H
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8, NA0:NA2
M, N
nP_LOAD
t
S_LOAD
S
t
H
Time
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
2
ICS843034AY-06 REV. A MARCH 7, 2007
ICS843034-06
FEMTOCLOCKS™ MULTI-RATE 3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
T
ABLE
1. SSM O
PERATION
SS Bit Pattern
SS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Operation*
Mode
off
center
center
center
center
center
center
center
off
down
down
down
down
down
down
down
%
0
±0.25
±0.25
±0.5
±0. 5
±1.0
±1.0
±1.5
0
-0.25
-0.25
-0.5
-0.5
-1.0
-1.0
-1.5
*NOTE: Estimated values with VCO frequency of 666.66MHz.
S
PREAD
S
PECTRUM
M
ODULATION
The ICS843034-06 offers the option of a spread spectrum
modulated output clock. The spread spectrum is controlled via
4 bits in the serial bit stream. These four bits configure the
SSM to be enabled and the amount of spread modulation to be
selected. See
Table 1
for the definition of the four bits. The four
additional bits are added at the beginning of the serial data
stream and are labeled SS3, SS2, SS1 and SS0. The initial
state of SS3, SS2, SS1 and SS0 is 0, 0, 0, 0 which places the
ICS843034-06 in the mode of spread spectrum off. Addition-
ally, a parallel load will result in spread spectrum modulation
being off. The ICS843034-06 offers down-spread or center-
spread using triangle-wave modulation.
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
3
ICS843034AY-06 REV. A MARCH 7, 2007
ICS843034-06
FEMTOCLOCKS™ MULTI-RATE 3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
T
ABLE
2. P
IN
D
ESCRIPTIONS
Number
1, 41, 42,
43, 44,
45, 47, 48
2, 3, 4
5
6
7
8, 14
9, 10
11
12, 24
13
15, 16
17
18, 19
20
21
22
23
Name
M8, M0, M1,
M2, M3,
M4, M6, M7
RESERVED
OE_REF
OE_A
OE_B
V
CC
NA0, NA1
NA2
V
EE
TEST
FOUTA0,
nFOUTA0
V
CCO_A
FOUTB0,
nFOUTB0
V
CCO_B
REF_CLK
V
CCO_REF
nc
Type
Input
Unused
Input
Input
Input
Power
Input
Input
Power
Output
Output
Power
Output
Power
Output
Power
Unused
Pulldown
Description
M divider input. Data latched on LOW-to-HIGH transition of
nP_LOAD input. LVCMOS/LVTTL interface levels.
Reser ve pins.
Output enable. Controls enabling and disabling of REF_OUT output.
Pulldown
LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTA0,
Pullup
nFOUTA0 outputs. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTB0,
Pullup
nFOUTB0 outputs. LVCMOS/LVTTL interface levels.
Core supply pins.
Determines output divider value as defined in Table 3C,
Pulldown Function Table. LVCMOS/LVTTL interface levels.
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode.
LVCMOS/LVTTL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Output supply pin for FOUTA0, nFOUTA0.
Differential output for the synthesizer. LVPECL interface levels.
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