July 2004
®
AS7C33512NTF18A
3.3V 512K×18 Flowthrough Synchronous SRAM with NTD
TM
Features
• Organization: 524,288 words × 18 bits
• NTD
™1
architecture for efficient bus operation
• Fast clock to data access: 6.5/7.5 ns
• Fast OE access time: 3.5 ns
• Fully synchronous operation
• Flow-through mode
• Asynchronous output enable control
1. NTD is a trademark of Alliance Semiconductor Corporation.
All
trademarks mentioned in this document are the property of their respective
owners.
• Available in 100-pin TQFP
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3 core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• 30 mW typical standby power
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic Block Diagram
A[18:0]
19
D
Address
register
burst logic
Q
19
CLK
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
FT
LBO
ZZ
18
CLK
D
Q
19
Write delay
addr. registers
CLK
Control
logic
CLK
Write Buffer
512K x 18
SRAM
array
DQ [a,b]
D
Data
Q
input
register
CLK
18
18
18
18
CLK
CEN
OE
Output
buffer
18
OE
DQ [a,b]
Selection Guide
–65
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
7.5
6.5
250
120
30
-75
8.5
7.5
225
100
30
Units
ns
ns
mA
mA
mA
7/12/04, v. 1.0
Alliance Semiconductor
P. 1 of 14
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33512NTF18A
®
Pin arrangement for TQFP (top view)
A
A
CE0
CE1
NC
NC
BWb
BWa
CE2
V
DD
V
SS
CLK
R/
W
CEN
OE
ADV/LD
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
A
7/12/04, v. 1.0
LBO
A
A
A
A
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
V
DDQ
V
SSQ
NC
NC
DQb0
DQb1
V
SSQ
V
DDQ
DQb2
DQb3
V
SS
V
DD
V
DD
V
SS
DQb4
DQb5
V
DDQ
V
SSQ
DQb6
DQb7
DQpb
NC
V
SSQ
V
DDQ
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TQFP 14 × 20mm
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SSQ
NC
DQpa
DQa7
DQa6
V
SSQ
V
DDQ
DQa5
DQa4
V
SS
NC
V
DD
ZZ
DQa3
DQa2
V
DDQ
V
SSQ
DQa1
DQa0
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
Alliance Semiconductor
P. 2 of 14
AS7C33512NTF18A
®
Functional description
The AS7C33512NTF18A family is a high performance CMOS 8 Mbit synchronous Static Random Access Memory (Flowthrough SRAM)
organized as 524,288 words × 18 bits and incorporates a LATE Write.
This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTD
™
) architecture, featuring an enhanced write operation
that improves bandwidth over pipelined burst devices. In a normal flowthrough burst device, the write data, command, and address are all
applied to the device on the same clock edge. If a read command follows this write command, the system must wait for one 'dead' cycle for
valid data to become available. This dead cycle can significantly reduce overall bandwidth for applications requiring random access or read-
modify-write operations.
NTD
™
devices use the memory bus more efficiently by introducing a write latency that matches one-cycle flow-through read latency. Write
data is applied one cycle after the write command and address, allowing the read pipeline to clear. With NTD
™
, write and read operations
can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18 bit writes.
Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device one clock
cycle later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for
normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select,
R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations,
including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C33512NTF18A operates with a 3.3V ± 5% power supply for the device core (V
DD
). DQ circuits use a separate power supply
(V
DDQ
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP package
Capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Test conditions
V
in
= 0V
V
in
= V
out
= 0V
Min
-
-
Max
5
7
Unit
pF
pF
TQFP thermal resistance
Description
Thermal resistance
(junction to ambient)
1
Thermal resistance
(junction to top of case)
1
1 This parameter is sampled
Conditions
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
1–layer
4–layer
Symbol
θ
JA
θ
JA
θ
JC
Typical
40
22
8
Units
°C/W
°C/W
°C/W
7/12/04, v. 1.0
Alliance Semiconductor
P. 3 of 14
AS7C33512NTF18A
®
Signal descriptions
Signal
CLK
CEN
A, A0, A1
DQ[a,b]
CE0, CE1,
CE2
ADV/LD
R/W
BW[a,b]
OE
LBO
ZZ
NC
I/O Properties Description
I
I
I
I/O
I
I
I
I
I
I
I
-
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
ASYNC
-
Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.
Clock enable. When de-asserted high, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is high.
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When low, a new
address is loaded.
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
Asynchronous output enable. I/O pins are not driven when OE is inactive.
Selects Burst mode. When tied to V
DD
or left floating, device follows Interleaved Burst
order. When driven Low, device follows linear Burst order.
This signal is internally pulled
High.
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connects. Note that pin 84 will be used for future address expansion to 16Mb density.
Burst Order
Interleaved Burst Order LBO=1
A1 A0 A1 A0 A1 A0 A1 A0
Starting Address
First increment
Second increment
Third increment
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Starting Address
First increment
Second increment
Third increment
Linear Burst Order LBO=0
A1 A0 A1 A0 A1 A0 A1 A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
7/12/04, v. 1.0
Alliance Semiconductor
P. 4 of 14
AS7C33512NTF18A
®
Synchronous truth table
[5,6,7,8,9
]
CE0
CE1 CE2 ADV/LD R/W
BWn
OE
CEN
Address
source
CLK
Operation
DQ
Notes
H
X
X
X
L
X
L
X
L
X
L
X
X
X
X
L
X
H
X
H
X
H
X
H
X
X
X
H
X
X
L
X
L
X
L
X
L
X
X
L
L
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
H
X
H
X
L
X
L
X
X
X
X
X
X
X
X
X
X
L
L
H
H
X
X
X
X
X
L
L
H
H
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
H
NA
NA
NA
NA
Next
Next
Next
L to H
L to H
L to H
L to H
L to H
L to H
L to H
DESELECT Cycle
DESELECT Cycle
DESELECT Cycle
CONTINUE DESELECT Cycle
READ Cycle (Begin Burst)
READ Cycle (Continue Burst)
DUMMY READ (Continue Burst)
WRITE CYCLE (Begin Burst)
WRITE CYCLE (Continue Burst)
High-Z
High-Z
High-Z
High-Z
Q
Q
1,10
2
3
1,3,10
2,3
1,2,3,
10
4
1
External L to H
External L to H NOP/DUMMY READ (Begin Burst) High-Z
External L to H
D
D
High-Z
High-Z
-
High-Z 1,2,10
External L to H NOP/WRITE ABORT (Begin Burst)
Next
L to H
WRITE ABORT (Continue Burst)
INHIBIT CLOCK
Current L to H
Key:
X = Don’t Care, H = HIGH, L = LOW.
BWn = H means all byte write signals (BWa and BWb
) are HIGH.
BW
n = L means one or more byte
write signals are LOW.
Notes:
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chose in the initial
BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.
2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a
WRITE command is given, but no operation is performed.
3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE
cycle. OE may be used when the bus turn-on and turn-off times do not meet an application’s requirements.
4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will
remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.
5
BW
a enables WRITEs to byte “a” (DQa pins/balls);
BW
b enables WRITEs to byte “b” (DQb pins/balls).
6 All inputs except
OE
and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
7 Wait states are inserted by setting
CEN
HIGH.
8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
10 The address counter is incremented for all CONTINUE BURST cycles.
7/12/04, v. 1.0
Alliance Semiconductor
P. 5 of 14
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