DS1045
DS1045
4–Bit Dual Programmable Delay Line
FEATURES
PIN ASSIGNMENT
IN
V
CC
EA
A0
A1
A2
A3
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
EB
OUTB
IN
B0
B1
B2
B3
OUTA
V
CC
EA
A0
A1
A2
A3
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
EB
OUTB
B0
B1
B2
B3
OUTA
•
All–silicon time delay
•
Two programmable outputs from a single input pro-
duce output–to–output delays between 9 and 84 ns
depending on device type
•
Programmable via four input pins
•
Programmable increments of 2 to 5 ns with a mini-
mum of 9 ns and a maximum of 84 ns
•
Output
pulse is a reproduction of input pulse after
delay with both leading and trailing edge accuracy
•
Standard 16–pin DIP or surface mount 16–pin SOIC
•
Auto–insertable
•
Low–power CMOS design is TTL–compatible
DS1045 16–PIN DIP
See Mech. Drawings
Section
DS1045S 16–PIN SOIC (300 MIL)
See Mech. Drawings
Section
PIN DESCRIPTION
IN
OUTA, OUTB
A0–A3
B0–B3
EA, EB
V
CC
GND
–
–
–
–
–
–
–
Delay Line Input
Delay Line Outputs
Parallel Program Inputs for OUT1
Parallel Program Inputs for OUT2
Enable A and B Inputs
+5 Volt Input
Ground
DESCRIPTION
The DS1045 is a programmable silicon delay line hav-
ing one input and two 4–bit programmable delay out-
puts. Each 4–bit programmable output offers the user
16 possible delay values to select from, starting with a
minimum inherent DS1045 delay of 9 ns and a maxi-
mum achievable delay in the standard DS1045 family of
84 ns. The standard DS1045 product line provides the
user with four devices having uniform delay increments of
2, 3, 4, and 5 ns depending on the device. Table 1 pres-
ents standard device family and delay capability. Addi-
tionally, custom delay increments are available for spe-
cial order through Dallas Semiconductor.
The DS1045 is TTL and CMOS–compatible and capa-
ble of driving ten 74LS–type loads. The output produced
by the DS1045 is both rising and falling edge precise.
The DS1045 programmable silicon delay line has been
designed as a reliable, economic alternative to hybrid
programmable delay lines. It is offered in a standard
16–pin auto–insertable DIP and a space–saving sur-
face mount 16–pin SOIC package.
021798 1/6
DS1045
PARALLEL PROGRAMMING
Parallel programming of the DS1045 is accomplished
via the set of parallel inputs A0–A3 and B0–B3 as shown
in Figure 1. Parallel input A0–A3 and B0–B3 accept TTL
levels and are used to set the delay values of outputs
OUTA and OUTB, respectively. Sixteen possible delay
values between the minimum 9 ns delay and the maxi-
mum delay of the DS1045–x device version can be se-
lected using the parallel programming inputs A0–A3 or
B0–B3 (see Table 2, “Delay vs. Programmed Input”).
For example, the DS1045–3 outputs OUTA or OUTB
and can be programmed to produce 16 possible delays
between the 9 ns (minimum) and the 54 ns (maximum)
in 3 ns increment levels.
For applications that do not require frequent reprogram-
ming, the parallel inputs can be set using fixed logic lev-
els, as would be produced by jumpers, DIP switches, or
TTL levels as produced by computer systems. Maxi-
mum flexibility in parallel programming can be achieved
when inputs are set by computer–generated data. By
using the enable input pins for each respective pro-
grammed output and observing the input setup (t
DSE
)
and hold time (t
DHE
) requirements, data can be latched
on an 8–bit bus. If the enable pins, EA and EB, are not
used to latch data, they should be set to a logic level 1.
After each change in the programmed delay value, a
settling time (t
EDV
) or (t
PDV
) is required before the
delayed output signal is reliably produced. Since the
DS1045 is a CMOS design, undefined input pins should
be connected to well defined logic levels and not left
floating.
PART NUMBER TABLE
Table 1
PART NUMBER
DS1045–2
DS1045–3
DS1045–4
DS1045–5
STEP ZERO DELAY
9
±
1 ns
9
±
1 ns
9
±
1 ns
9
±
1 ns
MAX DELAY TIME
39 ns
54 ns
69 ns
84 ns
MAX DELAY TOLERANCE
±1.8
ns
±2.5
ns
±3.3
ns
±4.1
ns
NOTE:
Additional delay step times are available from Dallas Semiconductor by special order. Consult factory for availability.
BLOCK DIAGRAM
Figure 1
EB
SELECT – MULTIPLEXER B
B0, B1, B2, B3
OUTB
IN
0
1
2
13
14
15
EA
SELECT – MULTIPLEXER A
A0, A1, A2, A3
OUTA
021798 2/6
DS1045
DELAY VS. PROGRAMMED VALUE
Table 2
PART NUMBER
DS1045–2
DS1045–3
DS1045–4
DS1045–5
9
9
9
9
11
12
13
14
13
15
17
19
15
18
21
24
17
21
25
29
19
24
29
34
OUTPUT DELAY VALUE
21
27
33
39
23
30
37
44
25
33
41
49
27
36
45
54
29
39
49
59
31
42
53
64
33
45
57
69
35
48
61
74
37
51
65
79
39
54
69
84
PROGRAM VALUES FOR EACH DELAY VALUE
A0 OR B0
A1 OR B1
A2 OR B2
A3 OR B3
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
0
1
1
1
0
1
1
0
1
1
1
1
1
1
1
DS1045 TEST CIRCUIT
Figure 2
Z o
+
50W
DUT
DS1045
PULSE
GENERATOR
IN
OUTA
OUTB
TIME
INTERVAL
COUNTER
Z o
+
50W
A0 – A3
B0 – B3
COMPUTER
IEEE 488 BUS
NOTE: BOTH OUTPUTS ARE TESTED IN THE
SAME MANNER.
74F04
TEST SETUP DESCRIPTION
Figure 2 illustrates the hardware configuration used for
measuring the timing parameters of the DS1045. The
input waveform is produced by a precision pulse gener-
ator under software control. Time delays are measured
by a time interval counter (20 ps resolution) connected
to the output. The DS1045 parallel inputs are controlled
by an interface to a central computer. All measurements
are fully automated with each instrument controlled by
the computer over an IEEE 488 bus.
021798 3/6
DS1045
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
Short Circuit Output Current
–1.0V to +7.0V
0°C to 70°C
–55°C to +125°C
250°C for 10 seconds
50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Voltage
Input Logic 1
Input Logic 0
Input Leakage
Active Current
Logic 1 Output
Current
Logic 0 Output
Current
SYMBOL
V
CC
V
IH
V
IL
I
I
I
CC
I
OH
I
OL
0 < V
I
< V
CC
V
CC
=5.25V
PERIOD=1
µs
V
CC
= 4.75V V
OH
= 4.0V
V
CC
= 4.75V V
OL
= 0.5V
8
TEST CONDITION
MIN
4.75
2.2
–0.5
–1.0
TYP
5.0
MAX
5.25
V
CC
+
0.5
0.8
+1.0
35.0
–1.0
V
V
(0°C to 70°C)
UNITS
NOTES
1
1
1
mA
µA
mA
mA
mA
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Period
Pulse Width
Input to Output Delay
Parallel Input Change to Delay In-
valid
Parallel Input Valid to Delay Valid
Enable Width
Data Setup to Enable
Data Hold from Enable
Enable to Delay Invalid
Enable to Delay Valid
SYMBOL
t
PERIOD
t
WI
t
PLH,
t
PHL
t
PDX
t
PDV
t
EW
t
DSE
t
DHE
t
EDX
t
EDV
15
10
0
5
15
0
10
MIN
4 x t
WI
100% of output delay size
Table 1
TYP
(0°C to 70°C; V
CC
5V + 5%)
MAX
UNITS
ns
NOTES
2
ns
ns
ns
ns
ns
ns
ns
CAPACITANCE
PARAMETER
Input Capacitance
SYMBOL
C
IN
MIN
TYP
MAX
10
UNITS
pF
(T
A
= 25°C)
NOTES
021798 4/6
DS1045
TEST CONDITIONS
T
A
=
25°C
±
3°C
5.0V
±
0.1V
V
CC
=
Input Pulse = 3.0V high to 0.0V low
±
0.1V
Input Source Impedance = 50 ohms maximum
Rise and fall times = 3.0 ns max. between 0.6V and 2.4V
Pulse Width = 250 ns
Period = 500 ns
Output Load = 74F04
Measurement Point = 1.5V on inputs and outputs
Output Load Capacitance = 15 pF
NOTE:
Above conditions are for test only and do not restrict the
operation of the device under other data sheet condi-
tions.
TIMING DIAGRAM: NON–LATCHED PARALLEL MODE, EA, EB = V
IH
PARALLEL
INPUTS
A0–A3, B0–B3
PREVIOUS VALUE
t
PDX
DELAY
TIME
PREVIOUS VALUE
TIMING DIAGRAM: LATCHED PARALLEL MODE
t
EW
ENABLE
EA, EB
t
DSE
PARALLEL
INPUTS
A0–A3, B0–B3
NEW VALUE
t
DHE
DELAY
TIME
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
É
É
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
É
É
t
EDX
PREVIOUS VALUE
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
t
EDV
NEW VALUE
t
PDV
NEW VALUE
NEW VALUE
021798 5/6
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