All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
Page 1 |
MK-Q-B-P-D-110410-03-2
DSC1103
DSC1123
Low-Jitter Precision LVDS Oscillator
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Ordering Code
Unit
V
V
°C
°C
°C
V
40sec max.
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Condition
Enable Modes
0: Enable/Standby
2: Enable/Disable
Temp Range
E: -20 to 70
I: -40 to 85
Packing
T: Tape & Reel
: Tube
DSC11
0
3
C I 5
Package
A: 7.0x5.0mm
B: 5.0x3.2mm
C: 3.2x2.5mm
-
156.2500
T
Freq (MHz)
156.2500
Stability
1: ±50ppm
2: ±25ppm
5: ±10ppm
Note: 1000+ years of data retention on internal memory
Specifications
Parameter
Supply Voltage
1
Supply Current
V
DD
I
DD
EN pin low – outputs are disabled
DSC1103
DSC1123
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
1 year @25°C
T=25°C
0.75xV
DD
-
DSC1103
DSC1123
Pull-up resistor exist
40
29
1.125
350
200
10
48
2.5
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
0.28
0.4
1.7
460
52
32
1.4
50
Single-Ended
20% to 80%
R
L
=50Ω, C
L
= 2pF
Single Frequency
Differential
Condition
Min.
2.25
Typ.
Max.
3.6
0.095
22
±10
±25
±50
±5
5
-
0.25xV
DD
5
5
20
Unit
V
mA
20
Frequency Stability
Aging
Startup Time
2
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
3
Output Enable Time
Enable Pull-Up Resistor
4
Supply Current
Output offset Voltage
Delta Offset Voltage
Pk to Pk Output Swing
Output Transition time
3
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
Integrated Phase Noise
Notes:
1.
2.
3.
4.
Δf
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
ppm
ppm
ms
V
ns
ms
ns
kΩ
mA
V
mV
mV
ps
MHz
%
ps
RMS
ps
RMS
LVDS Outputs
I
DD
V
OS
∆V
OS
Output Enabled, R
L
=50Ω
R=100Ω Differential
V
PP
t
R
t
F
f
0
SYM
J
PER
J
PH
2
Pin 6 V
DD
should be filtered with 0.1uf capacitor.
t
su
is time to 100ppm of output frequency after V
DD
is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Output is enabled if pad is floated or not connected.
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
Page 2 |
MK-Q-B-P-D-110410-03-2
DSC1103
DSC1123
Low-Jitter Precision LVDS Oscillator
Nominal Performance Parameters
(Unless specified otherwise: T=25° C, V
DD
=3.3 V)
0
-10
2.5
50-mV
Phase Jitter (ps RMS)
156MHz-LVDS
2.0
Rejection (dBc)
-20
-30
-40
-50
-60
-70
-80
0.1
1
10
100
100-mV
212MHz-LVDS
320MHz-LVDS
1.5
410MHz-LVDS
1.0
0.5
0.0
1000
10000
0
200
400
600
800
1000
Supply Noise Frequency (kHz)
Low-end of integration BW: x kHz to 20 MHz
Power supply rejection ratio
Phase jitter (integrated phase noise)
Output Waveform
t
R
t
F
Output
Output
80
%
50%
20%
350 mV
830 mv
1/
f
o
t
EN
t
DA
V
IH
Enable
V
IL
Typical Termination Scheme
V
DD
0.1uF
6
2
3
5
4
100 Ω
100 Ω
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
Page 3 |
MK-Q-B-P-D-110410-03-2
DSC1103
Test Circuit
DSC1123
Low-Jitter Precision LVDS Oscillator
Solder Reflow Profile
ax
260
°
C
Temperature (°C)
cM
.
20-40
Sec
217
°
C
200
°
C
ax
.
60-150
Sec
150
°
C
3C
/Se
60-180
Sec
cM
Reflow
Pre heat
8 min max
Cool
Time
25
°
C
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp) 3°C/Sec Max.
Preheat Time 150°C to 200°C
60-180 Sec
Time maintained above 217°C
60-150 Sec
255-260°C
Peak Temperature
Time within 5°C of actual Peak
20-40 Sec
6°C/Sec Max.
Ramp-Down Rate
Time 25°C to Peak Temperature
8 min Max.
3C
/
Se
S
S
S
6C
6C
6C/
M
cM
cM
ec
a.
a.
a x.
External Dimensions
Package Dimensions
units: mm[inch]
7.00
5
4
4
2.54
7.0 x 5.0
1.40
mm Plastic Package
5
6
1.10
5.00
3.70
1.80
2
3
3
2
1
2.80
0.85
No.
1
2
3
4
5
6
Pin terminal
Enable
nc
GND
Output
Output
VDD
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
Page 4 |
MK-Q-B-P-D-110410-03-2
DSC1103
DSC1123
Low-Jitter Precision LVDS Oscillator
5.0 x 3.2 mm Plastic Package
3.2 x 2.5 mm Plastic Package
DISCERA, Inc.
●
Phone: +1 (408) 432-8600
1961 Concourse Drive,
San Jose, California
95131
●
Fax: +1 (408) 432-8609 ● Email: sales@discera.com
●
●
USA
www.discera.com
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
EtherCAT（Ethernet for Control Automation Technology）是一种基于以太网的开发构架的实时工业现场总线通讯协议，EtherCAT是最快的工业以太网技术之一，同时它提供纳秒级精确同步。相对于设置了相同循环时间的其他总线系统，EtherCAT系统结构通常能减少25%-30%的CPU负载，EtherCAT的出现为系统的实时性能和拓扑的灵活性树立了新的标准。...[详细]
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