INTEGRATED CIRCUITS
74CBT3245
Octal bus switch with output enable
Product specification
1998 Oct 06
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal bus switch with output enable
74CBT3245
FEATURES
•
Functionally equivalent to QS3245
•
Standard ’245-type pinout
•
5Ω switch connection between two ports
•
TTL compatible control input levels
•
Package options include plastic small outline (D), shrink small
outline (DB), thin shrink small outline (TSSOP)
DESCRIPTION
The 74CBT3245 provides eight bits of high-speed TTL-compatible
bus switching in a standard ’245 device pinout. The low on-state
resistance of the switch allows connections to be made with minimal
propagation delay.
The 74CBT3245 device is organized as one 8-bit switch. When
enable (OE) is low, the switch is on and port A is connected to port
B. When OE is high, the switch is open and a high-impedance state
exists between the two ports.
The 74CBT3245 is characterized for operation from –40°C to 85°C.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IO(OFF)
I
CCZ
PARAMETER
Propagation delay
An to Yn
Pin capacitance (OFF state)
Total supply current
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
O
= 3V or 0V
Outputs disabled; V
CC
=5.5V
6
TYPICAL
UNIT
ns
pF
µA
ORDERING INFORMATION
PACKAGES
20-Pin plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
OUTSIDE NORTH AMERICA
74CBT3245 D
74CBT3245 DB
74CBT3245 PW
NORTH AMERICA
74CBT3245 D
74CBT3245 DB
7CBT3245PW DH
DWG NUMBER
SOT163-1
SOT339-1
SOT360-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
1
SYMBOL
NC
OE
A1–A8
B1–B8
GND
V
CC
Ground (0V)
Positive supply voltage
NAME AND FUNCTION
No internal connection
Output enable input
NC
A1
A2
A3
A4
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
19
2, 3, 4, 5, 6, 7, 8, 9
18, 17, 16, 15, 14,
13, 12, 11
10
20
GND 10
SA00507
1998 Oct 06
2
853-2132 20140
Philips Semiconductors
Product specification
Octal bus switch with output enable
74CBT3245
LOGIC SYMBOL
FUNCTION TABLE
INPUT
INPUTS/OUTPUTS
A, B
A=B
Z
OE
L
A1
2
18
B1
A8
9
11
H
B8
H = High voltage level
L = Low voltage level
Z = High impedance “off ” state
OE
19
SA00508
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Storage temperature range
V
O
< 0
output in Off or High state
output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +7.0
–50
–0.5 to +7.0
–50
–0.5 to +7
128
–65 to 150
UNIT
V
mA
V
mA
V
mA
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
T
amb
DC supply voltage
High-level input voltage
Low-level Input voltage
Operating free-air temperature range
–40
PARAMETER
Min
4.0
2.0
0.8
+85
Max
5.5
V
V
V
°C
UNIT
1998 Oct 06
3
Philips Semiconductors
Product specification
Octal bus switch with output enable
74CBT3245
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= –40°C to +85°C
Min
V
IK
I
I
I
CC
∆I
CC
C
I
C
IO(OFF)
r
on3
Input clamp voltage
Input leakage current
Quiescent supply
current
2
Additional supply current per
input pin
2
Control pins
Power-off leakage current
V
CC
= 4.5V; I
I
= –18mA
V
CC
= 5.5V; V
I
= GND or 5.5V
V
CC
= 5.5V; I
O
= 0, V
I
= V
CC
or GND
V
CC
= 5.5V, one input at 3.4V, other inputs at
V
CC
or GND
V
I
= 3V or 0, OE = V
CC
V
O
= 3V or 0
V
CC
= 4.5V; V
1
= 0V; I
I
= 64mA
On-resistance
V
CC
= 4.5V; V
1
= 0V; I
I
= 30mA
V
CC
= 4.5V; V
1
= 2.4V; I
I
= 15mA
3
6
5
5
10
7
7
15
Ω
Typ
1
Max
–1.2
±5
50
3.5
V
µA
µA
mA
pF
pF
UNIT
NOTES:
1. All typical values are at V
CC
= 5V, TA = 25 C
2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND
3. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch.
On-state resistance is determined by the lowest voltage of the two (A or B) terminals.
AC CHARACTERISTICS
GND = 0V; t
R;
C
L
= 50pF
74CBT3245
SYMBOL
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
T
amb
= –40°C to +85°C
V
CC
= +5.0V
±0.5V
Min
t
pd
t
en
t
dis
Propagation delay
1
Output enable time
to High and Low level
Output disable time
from High and Low level
A or B
OE
OE
B or A
A or B
A or B
Max
.25
ns
ns
ns
UNIT
NOTES:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
1998 Oct 06
4
Philips Semiconductors
Product specification
Octal bus switch with output enable
74CBT3245
AC WAVEFORMS
V
M
= 1.5V, V
IN
= GND to 3.0V
3V
3V
1.5V
INPUT
0V
t
PLH
t
PHL
V
OH
1.5V
OUTPUT
V
OL
Output
Waveform 2
S1 at Open
(see Note)
1.5V
Output
Waveform 1
S1 at 7 V
(see Note)
t
PZH
t
PZL
t
PLZ
1.5V
Output Control
(Low-level
enabling
1.5 V
1.5 V
0V
3.5V
1.5 V
t
PHZ
V
OH
– 0.3V
1.5 V
0V
Note:
Waveform 1 is for an output with internal conditions such that
the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is high except when disabled by the output control.
V
OL
+ 0.3V
V
OL
V
OH
SA00028
Waveform 1. Input to Output Propagation Delays
SA00029
Waveform 2. 3-State Output Enable and Disable Times
TEST CIRCUIT AND WAVEFORMS
7V
From Output
Under Test
C
L
= 50 pF
500
Ω
S1
Open
GND
500
Ω
Load Circuit
TEST
t
pd
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S1
open
7V
open
DEFINITIONS
Load capacitance includes jig and probe capacitance;
C
L
=
see AC CHARACTERISTICS for value.
SA00012
NOTES:
1. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, Z
O
= 50
Ω,
t
r
≤
2.5 ns, t
f
≤
2.5 ns.
2. The outputs are measured one at a time with one transition per measurement.
1998 Oct 06
5
FPGA/CPLD
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