CALIFORNIA MICRO DEVICES
PAC DN004
Applications
I/O port: protection for cellular phones,
notebooks computers, PDA, etc.
ESD protection for sensitive
electronic equipment.
ESD protection for applications where
low capacitive loading is required.
2 CHANNEL ESD PROTECTION ARRAY
Features
2-channel ESD protection
15KV ESD protection (HBM)
8KV contact discharge ESD protection
per IEC 61000-4-2
Low loading capacitance, 3 pF typ.
Miniature 4-pin SOT-143 package
Product Description
The PAC DN004 is a diode array designed to provide two channels of ESD protection for electronic components or sub-
systems. Each channel consists of a pair of diodes which steers the ESD current pulse either to the positive (V
P
) or negative
(V
N
) supply. The PAC DN004 will protect against ESD pulses up to 15 KV Human Body Model, and 8KV contact discharge
per International Standard IEC 61000-4-2.
This device has identical characteristics as the PAC DN006 (6 channel array). They can be used together in order to provide
a larger number of protected inputs if required. This device is particularly well-suited for portable electronics (e.g. cellular
phones, PDAs, notebook computers) because of its small package footprint, high ESD protection level, and low loading
capacitance. It is also suitable for protecting video output lines and I/O ports in computers and peripheral equipment.
ABSOLUTE MAXIMUM RATINGS
Diode Forward DC Current
(Note 1)
20mA
°
Storage Temperature
-65 C to 150
°
C
Operating Temperature Range
-20°C to 85°C
DC Voltage at any Channel Input V
N
-0.5V to V
P
+0.5V
Note 1: Only one diode conducting at a time.
SCHEMATIC CONFIGURATION
4
V
P
I/O 1
2
3
I/O 2
1
V
N
Parameter
Operating Supply Voltage ( V
P
- V
N
)
Supply Current, (V
P
- V
N
) = 5.5V, T=25°C
D iode Forward Voltage, I
F
= 20mA, T = 25°C
ESD Protection
Peak D ischarge Voltage at any Channel Input, in-system
(Note 2)
000
Human Body Model, Method 3015
(Note 3, 4)
000
Contact D ischarge per IEC 61000-4-2
(Note
5
)
Channel Clamp Voltage @ 15KV ESD HBM, T = 25°C
000
Positive transients
000
Negative transients
Channel Leakage Current, T = 25°C
Channel Input Capacitance (Measured @ 1 MHz)
V
P
= 5V, V
N
= 0V, V
IN
= 2 .5 V
(Note 4)
Package Power Rating
Note
Note
Note
Note
2:
3:
4:
5:
STANDARD SPECIFICATIONS
Min.
0.65 V
±15 KV
±8 KV
Typ.
Max.
5.5 V
10 µ A
0.95 V
(Notes 3, 4)
±0.1 µA
3pF
V
P
+ 13.0 V
V
N
- 13.0 V
±1.0 µA
6pF
225mW
From I/O pins to V
P
or V
N
only. V
P
bypassed to V
N
with 0.2
µF
ceramic capacitor.
Human Body Model per MIL-STD-883, Method 3015, C
Discharge
=100pF, R
Discharge
=1.5K
Ω
, V
P
=5.0V, V
N
=GND.
This parameter is guaranteed by characterization.
Standard IEC 61000-4-2 with C
Discharge
=150pF, and R
Discharge
=330
Ω
, V
P
=5V, V
N
=GND.
©1999 California Micro Devices Corp. All rights reserved.
P/Active
®
is a registered trademark and PAC is a trademark of California Micro Devices.
11/99
C0280498D
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
1
CALIFORNIA MICRO DEVICES
Input Capacitance vs. Input Voltage
5
PAC DN004
Input Capacitance (pF)
4
3
2
1
0
0
1
2
3
4
5
Input Voltage
Typical variation of C
IN
with V
IN
(V
P
= 5V, V
N
= 0V, 0.1µF chip capacitor between V
P
& V
N
)
ST
ANDAR
D PART ORDERING INFORMATION
Package
Ordering Part Number
Style
Part Marking
SOT-143
D N 004
Pins
4
When placing an order please specify desired shipping: Tubes or Tape & Reel.
Application Information
See also California Micro Devices Application note AP209, Design Considerations for ESD protection.
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize
parasitic series inductances to the Supply and Ground rails. Refer to Figure 1, which illustrates the case of a positive
ESD pulse applied between an input channel and Chassis Ground. The parasitic series inductance back to the power
supply is represented by L
1
. The voltage V
Z
on the line being protected is:
V
Z
= Forward voltage drop of D
1
+ L
1
x d(I
esd
)/dt + V
Supply
where I
esd
is the ESD current pulse, and V
Supply
is the positive supply voltage.
Figure 1
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC 61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1nS. Here d(I
esd
)/dt can be
approximated by
∆I
esd
/∆t, or 30/(1x10
-9
). So just 10nH of series inductance (L
1
) will lead to a 300V increment in V
Z
!
©1999 California Micro Devices Corp. All rights reserved.
2
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
11/99
CALIFORNIA MICRO DEVICES
PAC DN004
Similarly for negative ESD pulses, parasitic series inductance from the V
N
pin to the ground rail will lead to drastically
increased negative voltage on the line being protected.
Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies
exhibit a much higher output impedance to fast transient current spikes. In the V
Z
equation above, the V
Supply
term, in
reality, is given by (V
DC
+ I
esd
x R
out
), where V
DC
and R
out
are the nominal supply DC output voltage and effective output
impedance of the power supply respectively. As an example, a R
out
of 1 ohm would result in a 10V increment in V
Z
for a
peak I
esd
of 10A.
To mitigate these effects, a high frequency bypass capacitor should be connected between the V
P
pin of the ESD Protection
Array and the ground plane. The value of this bypass capacitor should be chosen such that it will absorb the charge
transferred by the ESD pulse with minimal change in V
P
. Typically a value in the 0.1 µF to 0.2 µF range is adequate for
IEC-61000-4-2 level 4 contact discharge protection (8KV). For higher ESD voltages, the bypass capacitor should be
increased accordingly. Ceramic chip capacitors mounted with short printed circuit board traces are good choices for this
application. Electrolytic capacitors should be avoided as they have poor high frequency characteristics. For extra protection,
connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series inductance
inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher than the maximum supply
voltage.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V
P
pin of the
Protection Array as possible, with minimum PCB trace lengths to the power supply and ground planes to minimize stray
series inductance.
©1999 California Micro Devices Corp. All rights reserved.
11/99
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
3
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