CALIFORNIA MICRO DEVICES
PACVGA200
Pin Diagram
VGA PORT COMPANION CIRCUIT
Features
7 channels of ESD protection for all VGA port
connector pins meeting IEC-61000-4-2 Level-4 ESD
requirements (8KV contact discharge)
Very low loading capacitance from ESD protection
diodes on VIDEO lines, 4pF typical
TTL to CMOS level-translating buffers with power
down mode for HSYNC and VSYNC lines
75
Ω
termination resistors for VIDEO lines (matched
to 1% typ.)
Bi-directional level shifting N-channel FETs provided for
DDC_CLK & DDC_DATA channels
Compact 24-pin QSOP package
24-PIN QSOP PACKAGE
Product Description
The PACVGA200 incorporates 7 channels of ESD protection for all signal lines commonly found in a VGA port. ESD protection
is implemented with current steering diodes designed to safely handle the high surge currents encountered with IEC-1000-4-
2 Level-4 ESD Protection (8KV contact discharge). When a channel is subjected to an electrostatic discharge, the ESD current
pulse is diverted via the protection diodes into the positive supply rail or ground where it may be safely dissipated.
Separate positive supply rails are provided for the VIDEO, DDC and SYNC channels to facilitate interfacing with low voltage
Video Controller ICs and provide design flexibility in multi-supply-voltage environments.
Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the Video Controller IC (SYNC1, SYNC2).
These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and V
CC4
. These
drivers have nominal 60Ω output impedance to match the characteristic impedance of the HSYNC & VSYNC lines of the video
cables typically used in PC applications.
Two N-channel FETs provide the level shifting function required when the DDC controller is operated at a lower supply voltage
than the monitor.
Three 75Ω termination resistors suitable for terminating the video signals from the video DAC are also provided. These
resistors have separate input pins to allow insertion of additional EMI filtering, if required, between the termination point and
the ESD protection diodes. These resistors are matched to better than 2% for excellent signal level matching for the R/G/B
signals.
When the PWR_UP input is driven LOW the SYNC inputs can be floated without causing the SYNC buffers to draw any current
from the V
CC3
supply. When the PWR_UP input is LOW the SYNC outputs are driven LOW.
An internal diode (D1 in schematic below) is also provided so that V
CC3
can be derived from V
CC4
, if desired, by connecting V
CC3
to V_BIAS. In applications where V
CC4
may be powered down, diode D1 blocks any DC current paths from the DDC_OUT pins
back to the powered down V
CC4
rail via the top ESD protection diodes.
Schematic Diagram
© 2000 California Micro Devices Corp. All rights reserved. PACVGA200 is a trademark of California Micro Devices Corp.
4/00
C0641299
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
1
CALIFORNIA MICRO DEVICES
ABSOLUTE MAXIMUM RATINGS
Parameter
V
CC1
, V
CC2
, V
CC3
& V
CC4
supply voltage
D i o d e D 1 f o rwa rd c u rre n t
D C v o l ta g e a t i n p u ts :
V I D E O_ 1 , V I D E O_ 2 , V I D E O_ 3
T ER M_ 1 , T ER M_ 2 , T ER M_ 3
D D C_ I N 1 , D D C_ I N 2
D D C _ OU T 1 , D D C _ OU T 2
S Y N C_ I N 1 , S Y N C_ I N 2
Temperature:
Storage
Operating Ambient
Package power dissipation
-40 to +150
0 to +70
1.0
o
C
o
C
PACVGA200
Unit
V
uA
V
V
V
V
V
Rating
GND -0.5, +6.0
100
GND -0.5, V
CC1
+0.5
-6.0, +6.0
GND -0.5, V
CC2
+0.5
GND -0.5, V
CC3
+0.5
GND -0.5, V
CC4
+0.5
W
ELECTRICAL OPERATING CHARACTERISTICS
(over operating conditions unless specified other wise)
Symbol
Parameter
Conditions
MIN
TYP
MAX
UNIT
I
CC1
I
CC2, 3
I
CC4
V
CC1
s u p p l y c u rre n t
V
CC2
, V
CC3
s u p p l y c u rre n t
V
CC4
supply current
V
BIAS
R
T
V
IH
V
IL
V
OH
V
OL
R
b
, R
p
R
c
I
N
V
BIAS
open circuit voltage
V I D E O te r mi n a ti o n r e s i s ta n c e
R
T
r e s i s ta n c e ma tc h i n g
L o g i c H i g h i n p u t v o l ta g e
1
L o g i c L o w i n p u t v o l ta g e
1
L o g i c H i g h o u tp u t v o l ta g e
1
L o g i c L o w o u tp u t v o l ta g e
1
R e s i s to r v a l u e
V
CC 2
pull-down resistor
Input current
VID EO inputs
HSYNC, VSYNC inputs
V
CC1
= 5V; VID EO inputs at V
CC1
or GND
V
CC2
= V
CC3
= 5V
V
CC4
= 5V; SYNC inputs at GND or V
CC4
;
PWR_UP pin at V
CC4;
SYNC outputs unloaded
V
CC4
= 5V; SYNC inputs at 3.0V; PWR_UP
pin at V
CC4
; SYNC outputs unloaded
V
CC4
= 5V; PWR_UP input at GND ; SYNC
outputs unloaded
No external current drawn from V
BIAS
pin
71.25
V
CC4
= 5 .0 V
V
CC4
= 5 .0 V
I
OH
= -4mA, V
CC4
= 5.0V
I
OL
= 4mA, V
CC4
= 5.0V
PWR_UP, V
CC3
= 5.0V
V
CC2
= 3.0V
V
CC1
= 5V; V
IN
= V
CC1
or GND
V
CC4
= 5V; V
IN
= V
CC4
or GND
(V
CC2
- V
DDC_IN
) < 0.4V; V
DDC
_
OUT
= V
CC2
(V
CC2
- V
DDC_OUT
) < 0.4V; V
DDC
_
IN
= V
CC2
V
CC2
= 2.5V; V
S
= GND , I
DS
= 3mA
2.0
10
10
10
200
10
V
CC4
-0.8
75
1
78.75
2
0.8
4.4
0.5
0.5
1
1.5
0.4
2
3
±1
±1
10
10
0.15
uA
uA
uA
uA
uA
V
Ω
%
V
V
V
V
MΩ
MΩ
µA
µA
µA
µA
V
I
OFF
V
ON
C
IN
OFF state leakage current, level
shifting NFET
Voltage drop across level
shifting NFET when turned ON
Input capacitance
3
VID EO_1, VID EO_2, VID EO_3
t
PLH
t
PHL
t
r
, t
f
V
ESD
Note 1:
Note 2:
V
CC1
= 5 .0 V ; V
IN
= 2 .5 V ; me a s u re d a t 1 M H z
V
CC1
= 2.5V; V
IN
= 1.25V; measured at 1MHz
SYNC drivers L-H propagation delay C
L
= 5 0 p F; V
CC
= 5 V ; I n p u t t
r
a n d t
f
< 5 n s
SYNC drivers H-L propagation delay C
L
= 5 0 p F; V
CC
= 5 V ; I n p u t t
r
a n d t
f
< 5 n s
SYNC drivers output rise & fall times C
L
= 5 0 p F; V
CC
= 5 V ; I n p u t t
r
a n d t
f
< 5 n s
ESD withstand voltage
2, 3
V
CC1
= V
CC3
= V
CC4
= 5V
4.0
4.5
8
8
7
±8
pF
12
12
ns
ns
ns
kV
These parameter applies only to the HSYNC and VSYNC channels.
Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. V
CC1
, V
CC3
and V
CC4
must be bypassed
to GND via a low impedance ground plane with a 0.2uF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse
is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins
are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 and DDC_OUT2. All other pins are ESD
protected to the industry standard 2kV per the Human Body model (MIL-STD-883, Method 3015).
This parameter is guaranteed by design and characterization.
Note 3:
©2000 California Micro Devices Corp. All rights reserved.
2
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
4/00
CALIFORNIA MICRO DEVICES
Typical Connection Diagram
PACVGA200
A resistor may be necessary between the V
CC3
pin and ground if protection against a stream of ESD pulses is required
while the PACVGA200 is in the power-down state. The value of this resistor should be chosen such that the extra
charge deposited into the V
CC3
bypass capacitor by each ESD pulse will be discharged before the next ESD pulse occurs.
The maximum ESD repetition rate specified by the IEC-61000-4-2 standard is one pulse per second. When the PACVGA200
is in the power-up state, an internal discharge resistor is connected to ground via an FET switch for this purpose.
For the same reason, V
CC1
and V
CC4
may also require bypass capacitor discharging resistors to ground if there are no
other components in the system to provide a discharge path to ground.
GNDA, the reference voltage for the 75R resistors is not connected internally to GNDD and should ideally be connected
to the ground of the video DAC IC.
Pins
24
ST
ANDAR
D PART ORDE RING INFORMATION
Package
Ordering Part Number
Style
Part Marking
QSOP
PACVGA200Q
When placing an order please specify desired shipping: Tubes or Tape & Reel.
© 2000 California Micro Devices Corp. All rights reserved.
4/00
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
3
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