CALIFORNIA MICRO DEVICES
PACVGA201
Pin Diagram
VGA PORT COMPANION CIRCUIT
Features
7 channels of ESD protection for all VGA port
connector pins meeting IEC-61000-4-2 Level-4 ESD
requirements (8KV contact discharge)
Very low loading capacitance from ESD protection
diodes on VIDEO lines, 4pF typical
TTL to CMOS level-translating buffers with power
down mode for HSYNC and VSYNC lines
Three power supplies for design flexibility
Compact 16-pin QSOP package
16-PIN QSOP PACKAGE
Product Description
The PACVGA201 incorporates 7 channels of ESD protection for all signal lines commonly found in a VGA port. ESD protection
is implemented with current steering diodes designed to safely handle the high surge currents encountered with IEC-61000-4-
2 Level-4 ESD Protection (8KV contact discharge). When a channel is subjected to an electrostatic discharge, the ESD current
pulse is diverted via the protection diodes into the positive supply rail or ground where it may be safely dissipated.
Separate positive supply rails are provided for the VIDEO, DDC_OUT and SYNC channels to facilitate interfacing with low
voltage video controller ICs and provide design flexibility in multiple-supply-voltage environments.
An internal diode (D1, in schematic below) is provided such that V
CC2
is derived from V
CC3
. (V
CC2
does not require an external
power supply input.) In applications where V
CC3
may be powered down, diode D1 blocks any DC current path from the
DDC_OUT pins back to the powered down V
CC3
rail via the upper ESD protection diodes.
Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the Video Controller IC (SYNC1, SYNC2).
These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and V
CC3
.
When the PWR_UP input is driven LOW the SYNC inputs can be floated without causing the SYNC buffers to draw any current
from the V
CC3
supply. When the PWR_UP input is LOW the SYNC outputs are driven LOW.
Schematic Diagram
© 2000 California Micro Devices Corp. All rights reserved. PAC VGA201 is a trademark of California Micro Devices Corp.
4/00
C0651299
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
1
CALIFORNIA MICRO DEVICES
ABSOLUTE MAXIMUM RATINGS
Parameter
V
CC1
, V
CC3
supply voltage
D C v o l ta g e a t i n p u ts :
V I D E O_ 1 , V I D E O_ 2 , V I D E O_ 3
D D C _ OU T 1 , D D C _ OU T 2
S Y N C_ I N 1 , S Y N C_ I N 2
Temperature:
Storage
Operating Ambient
Package power dissipation
-40 to +150
0 to +70
0.75
o
C
o
C
PACVGA201
Unit
V
V
V
V
V
Rating
GND -0.5, +6.0
GND -0.5, V
CC1
+0.5
GND -0.5, V
CC2
+0.5
GND -0.5, V
CC3
+0.5
W
Symbol
I
CC1
I
CC3
V
CC2
V
IH
V
IL
V
OH
V
OL
R
b
, R
p
I
N
ELECTRICAL OPERATING CHARACTERISTICS
(over operating conditions unless specified other wise)
Parameter
Conditions
MIN
V
CC1
s u p p l y c u rre n t
V
CC1
= 5V
V
CC3
supply current
V
CC3
= 5V; SYNC inputs at GND or V
CC3
;
PWR_UP pin at V
CC3;
SYNC outputs unloaded
V
CC3
= 5V; SYNC inputs at 3.0V; PWR_UP
pin at V
CC3
; SYNC outputs unloaded
V
CC3
= 5V; PWR_UP input at GND ; SYNC
outputs unloaded
V
CC2
pin open circuit voltage
V
CC2
voltage internally derived from V
CC3
via
d i o d e D 1 ; n o e x te rn a l c u rre n t d ra wn ;
L o g i c H i g h i n p u t v o l ta g e
1
V
CC3
= 5 .0 V
2.0
L o g i c L o w i n p u t v o l ta g e
1
V
CC3
= 5 .0 V
2
L o g i c H i g h o u tp u t v o l ta g e
I
OH
= -4mA, V
CC3
= 5.0V
4.4
L o g i c L o w o u tp u t v o l ta g e
2
I
OL
= 4mA, V
CC3
= 5.0V
R e s i s to r v a l u e
PWR_UP, V
CC3
= 5.0V
0.5
Input current
VID EO inputs
HSYNC, VSYNC inputs
V
CC1
= 5V; V
IN
= V
CC1
or GND
V
CC3
= 5V; V
IN
= V
CC3
or GND
TYP
MAX
UNIT
10
10
200
10
V
CC3
-0.8
uA
uA
uA
uA
V
V
V
V
V
MΩ
µA
µA
pF
0.8
0.4
2
±1
±1
4.0
4.5
8
8
7
1
C
IN
Input capacitance
4
VID EO_1, VID EO_2, VID EO_3
t
PLH
t
PHL
t
r
, t
f
V
ESD
Note 1:
Note 2:
Note 3:
V
CC1
= 5 .0 V ; V
IN
= 2 .5 V ; me a s u re d a t 1 M H z
V
CC1
= 2.5V; V
IN
= 1.25V; measured at 1MHz
SYNC drivers L-H propagation delay C
L
= 5 0 p F; V
CC3
= 5 V ; I n p u t t
r
a n d t
f
< 5 n s
SYNC drivers H-L propagation delay C
L
= 5 0 p F; V
CC3
= 5 V ; I n p u t t
r
a n d t
f
< 5 n s
SYNC drivers output rise & fall times C
L
= 5 0 p F; V
CC3
= 5 V ; I n p u t t
r
a n d t
f
< 5 n s
ESD withstand voltage
3, 4
V
CC1
= V
CC2
= V
CC3
= 5V
12
12
±8
ns
ns
ns
kV
These parameters apply only to SYNC_IN1, SYNC_IN2 and PWR_UP
.
These parameters apply only to SYNC_OUT1 and SYNC_OUT2.
Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. V
CC1
, V
CC2
and V
CC3
must be bypassed to GND via
a low impedance ground plane with a 0.2uF or greater, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied
between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: VIDEO_1,
VIDEO_2, VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 and DDC_OUT2. All other pins are ESD protected to the
industry standard 2kV per the Human Body model (MIL-STD-883, Method 3015).
This parameter is guaranteed by design and characterization.
Note 4:
©2000 California Micro Devices Corp. All rights reserved.
2
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
4/00
CALIFORNIA MICRO DEVICES
Typical Connection Diagram
PACVGA201
A resistor may be necessary between the V
CC2
pin and ground if protection against a stream of ESD pulses is required
while the PACVGA201 is in the power-down state. The value of this resistor should be chosen such that the extra
charge deposited into the V
CC2
bypass capacitor by each ESD pulse will be discharged before the next ESD pulse occurs.
The maximum ESD repetition rate specified by the IEC-61000-4-2 standard is one pulse per second. When the PACVGA201
is in the power-up state, an internal discharge resistor is connected to ground via a FET switch for this purpose.
For the same reason, V
CC1
and V
CC3
may also require bypass capacitor discharging resistors to ground if there are no
other components in the system to provide a discharge path to ground.
Pins
16
ST
ANDAR
D PART ORDE RING INFORMATION
Package
Ordering Part Number
Style
Part Marking
QSOP
PACVGA201Q
When placing an order please specify desired shipping: Tubes or Tape & Reel.
© 2000 California Micro Devices Corp. All rights reserved.
4/00
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
3
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
