SU572328FG8E6UU
December 7, 2005
Ordering Information
Part Numbers
SM572328FG8E6DB
SB572328FG8E6DB
Description
32Mx72 (256MB), DDR2, 240-pin DIMM, Registered, ECC,
32Mx8 Based, DDR2-400-333, 30.00mm, 22Ω DQ termination.
32Mx72 (256MB), DDR2, 240-pin DIMM, Registered, ECC,
32Mx8 Based, DDR2-400-333, 30.00mm, 22Ω DQ termination,
Lead-Free Module.
32Mx72 (256MB), DDR2, 240-pin DIMM, Registered, ECC,
32Mx8 Based, DDR2-400-333, 30.00mm, 22Ω DQ termination,
Green Module (RoHS Compliant).
32Mx72 (256MB), DDR2, 240-pin DIMM, Registered, ECC,
32Mx8 Based, DDR2-533-444, 30.00mm, 22Ω DQ termination.
32Mx72 (256MB), DDR2, 240-pin DIMM, Registered, ECC,
32Mx8 Based, DDR2-533-444, 30.00mm, 22Ω DQ termination,
Lead-Free Module.
32Mx72 (256MB), DDR2, 240-pin DIMM, Registered, ECC,
32Mx8 Based, DDR2-533-444, 30.00mm, 22Ω DQ termination,
Green Module (RoHS Compliant).
32Mx72 (256MB), DDR2, 240-pin DIMM, Registered, ECC,
32Mx8 Based, DDR2-667-555, 30.00mm, 22Ω DQ termination,
Green Module (RoHS Compliant).
Module Speed
PC2-3200 @ CL 3.0
PC2-3200 @ CL 3.0
SG572328FG8E6DB
PC2-3200 @ CL 3.0
SM572328FG8E6DG
SB572328FG8E6DG
PC2-4200 @ CL 4.0
PC2-4200 @ CL 4.0
SG572328FG8E6DG
PC2-4200 @ CL 4.0
SG572328FG8E6IL
PC2-5300 @ CL 5.0
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
1
SU572328FG8E6UU
December 7, 2005
Revision History
• December 7, 2005
Corrected the OCD Program in the EMRS on page 14.
Changed the Ambient Operating temperature to 0 to +65°C on page 16.
Added the Case Operating temperature on page 16.
• September 9, 2005
Corrected the DLL Enable in the EMRS on page 14.
• August 17, 2005
Added SG572328FG8E6DB, SG572328FG8E6DG & SG572328FG8E6IL to the Ordering Information on page 1.
• July 30, 2004
Changed module speed from PC2-4300 to PC2-4200 in accordance with the new Jedec standard.
• July 8, 2004
Datasheet released.
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
2
SU572328FG8E6UU
December 7, 2005
256MByte (32Mx72) DDR2 SDRAM Module - 32Mx8 Based
240-pin DIMM, Registered, ECC
Features
•
•
•
•
•
•
•
Standard
Configuration
Cycle Time
CAS# Latency
:
:
:
:
JEDEC
ECC
5.0ns (DDR2-400)
3.75ns (DDR2-533)
3.0ns (DDR2-667)
3.0, 4.0 (DDR2-400/533)
4.0, 5.0 (DDR2-667)
0, 1.0, 2.0, 3.0 & 4.0
Read (CAS#) Latency - 1
4, 8
•
•
•
•
•
•
•
•
•
Burst Type
:
Sequential/Interleave
No. of Internal
Banks per SDRAM :
4
Operating Voltage :
1.8V
Refresh
:
8K/64ms
Device Physicals :
FBGA
Lead Finish
:
Gold
Length x Height
:
133.35mm x 30.00mm
No. of sides
:
Single-sided
Mating Connector (Examples)
Vertical
:
Molex - 87705-0021
Posted CAS#/Additive
Latency (AL)
:
Write Latency (WL)
:
Burst Length
:
240-Pin DDR2 DIMM Pin List
Pin Pin
No. Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
RESET#
NC
V
SS
Pin Pin
No. Name
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CB2
CB3
V
SS
Pin Pin
No. Name
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
A4
V
DDQ
A2
V
DD
V
SS
V
SS
V
DD
DU
V
DD
A10/AP
BA0
V
DDQ
WE#
CAS#
V
DDQ
Pin Pin
No. Name
91
92
93
94
95
96
97
98
99
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
Pin Pin
No. Name
121 V
SS
122 DQ4
123 DQ5
124 V
SS
125 DM0
126 NC
127 V
SS
128 DQ6
129 DQ7
130 V
SS
131 DQ12
132 DQ13
133 V
SS
134 DM1
135 NC
136 V
SS
137 DU
138 DU
139 V
SS
140 DQ14
Pin Pin
No. Name
151 V
SS
152 DQ28
153 DQ29
154 V
SS
155 DM3
156 NC
157 V
SS
158 DQ30
159 DQ31
160 V
SS
161 CB4
162 CB5
163 V
SS
164 DM8
165 NC
166 V
SS
167 CB6
168 CB7
169 V
SS
170 V
DDQ
Pin Pin
No. Name
181 V
DDQ
182 A3
183 A1
184 V
DD
185 CK0
186 CK0#
187 V
DD
188 A0
189 V
DD
190 BA1
191 V
DDQ
192 RAS#
193 CS0#
194 V
DDQ
195 ODT0
196 A13 (NC)
197 V
DD
198 V
SS
199 DQ36
200 DQ37
Pin Pin
No. Name
211 DM5
212 NC
213 V
SS
214 DQ46
215 DQ47
216 V
SS
217 DQ52
218 DQ53
219 V
SS
220 DU
221 DU
222 V
SS
223 DM6
224 NC
225 V
SS
226 DQ54
227 DQ55
228 V
SS
229 DQ60
230 DQ61
100 V
SS
101 SA2
102 NC
103 V
SS
104 DQS6#
105 DQS6
CS1# (NC) 106 V
SS
ODT1 (NC) 107 DQ50
V
DDQ
V
SS
DQ32
108 DQ51
109 V
SS
110 DQ56
( All specifications of this module are subject to change without notice.)
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
3
SU572328FG8E6UU
December 7, 2005
240-pin DDR2 DIMM Pin List (Contd.)
Pin Pin
No. Name
21
22
23
24
25
26
27
28
29
30
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
Pin Pin
No. Name
51
52
53
54
55
56
57
58
59
60
V
DDQ
CKE0
V
DD
BA2 (NC)
DU
V
DDQ
A11
A7
V
DD
A5
Pin Pin
No. Name
81
82
83
84
85
86
87
88
89
90
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
Pin Pin
No. Name
111 DQ57
112 V
SS
113 DQS7#
114 DQS7
115 V
SS
116 DQ58
117 DQ59
118 V
SS
119 SDA
120 SCL
Pin Pin
No. Name
141 DQ15
142 V
SS
143 DQ20
144 DQ21
145 V
SS
146 DM2
147 NC
148 V
SS
149 DQ22
150 DQ23
Pin Pin
No. Name
Pin Pin
No. Name
Pin Pin
No. Name
231 V
SS
232 DM7
233 NC
234 V
SS
235 DQ62
236 DQ63
237 V
SS
238 V
DDSPD
239 SA0
240 SA1
171 CKE1 (NC) 201 V
SS
172 V
DD
173 A15 (NC)
174 A14 (NC)
175 V
DDQ
176 A12
177 A9
178 V
DD
179 A8
180 A6
202 DM4
203 NC
204 V
SS
205 DQ38
206 DQ39
207 V
SS
208 DQ44
209 DQ45
210 V
SS
Pin Description Table
Symbol
CK0
Type
SSTL_18
Polarity
Positive
Edge
Negative
Edge
Active High
Function
Positive line of the differential pair of system clock inputs. (All DDR2 SDRAM address and
control inputs are sampled on the rising edge of their associated clocks. Output data is ref-
erenced at the crossings of the clocks.)
Negative line of the differential pair of system clock inputs.
On-Die Termination: ODT when high enables termination resistance internal to the DDR2
SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, and
DM. The ODT input will be ignored if disabled in Extended Mode Register (EMRS).
Activates the DDR2 SDRAM CLK signal when high and deactivates the CLK signal when
low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self
Refresh mode.
Enables the associated DDR2 SDRAM command decoder when low and disables decoder
when high. When decoder is disabled, new commands are ignored but previous operations
continue.
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the
operations to be executed by the SDRAM.
Bank Address define to which bank an Activate, Read, Write or Precharge command is
being applied. Bank address also determines if the Mode Register or Extended Mode Reg-
ister is to be accessed during a MRS or EMRS cycle.
CK0#
ODT0
SSTL_18
SSTL_18
CKE0
SSTL_18
Active High
CS0#
SSTL_18
Active Low
RAS#, CAS#,
WE#
BA0, BA1
SSTL_18
SSTL_18
Active Low
-
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
4
SU572328FG8E6UU
December 7, 2005
Pin Description Table (Contd.)
Symbol
A0~A9,
A10/AP,
A11~A12
Type
SSTL_18
Polarity
-
Function
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, A10/AP is used
to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high,
autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to con-
trol which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the
state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to pre-
charge. The address inputs also provide the op-code during Mode Register Set com-
mands.
Data and Check Bit Input/Output pins.
SDRAM differential data strobe for input and output data.
SDRAM differential data strobe for input and output data.
DM is an input mask signal for write data. Input data is masked when DM is sampled high
coincident with that input data during a write access. DM is sampled on both edges of
DQS. Although DM pins are input only, the DM loading matches the DQ/DQS loading.
Slave Address Select for EEPROM. These pins are used to configure the presence-detect
device.
Serial Bus Data Line for EEPROM. SDA is a bidirectional pin used to transfer addresses
and data into and out of the presence-detect portion of the module. A resistor must be con-
nected from the SDA bus line to V
DD
to act as pull up on the system board.
Serial Bus Clock for EEPROM. SCL is used to synchronize the presence-detect data
transfer to and from the module. A resistor may be connected from the SCL bus line to
V
DD
to act as pull up on the system board.
Register and PLL control pin.When low, all register outputs will be driven low and the PLL
clocks to the DRAM and register will be set to low levels (the PLL will remain synchronized
with the input clock, if within spec range).
SDRAM positive power supply. 1.8V ±0.1V
Power supply return (ground).
SDRAM I/O reference supply.
SDRAM I/O Driver positive power supply. 1.8V ±0.1V
Serial EEPROM positive power supply (wired to a separate power pin at the connector
which supports operation from1.7 V to 3.6 V.
No Connect
Do not use
DQ0~DQ63
CB0~CB7
DQS0~DQS8
DQS0#~DQS8#
DM0~DM8
SSTL_18
SSTL_18
SSTL_18
SSTL_18
-
Positive
Edge
Negative
Edge
Active High
SA0~SA2
SDA
LVTTL
LVTTL
-
-
SCL
LVTTL
-
RESET#
LV-
CMOS
Supply
Supply
Supply
Supply
Supply
-
-
Active Low
V
DD
V
SS
V
REF
V
DDQ
V
DDSPD
NC
DU
-
-
-
-
-
-
-
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
5
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