CAT24C32
32-Kb I
2
C CMOS Serial EEPROM
FEATURES
Supports Standard and Fast I
2
C Protocol
1.7V to 5.5V Supply Voltage Range
32-Byte Page Write Buffer
Hardware Write Protection for entire memory
Schmitt Triggers and Noise Suppression Filters
on I
2
C Bus Inputs (SCL and SDA)
Low power CMOS technology
1,000,000 program/erase cycles
100 year data retention
Industrial and Extended temperature range
RoHS-compliant PDIP, SOIC, TSSOP, TDFN and
UDFN 8-lead packages
For Ordering Information details, see page 16.
DEVICE DESCRIPTION
The CAT24C32 is a 32-Kb CMOS Serial EEPROM
devices, internally organized as 128 pages of 32 bytes
each.
It features a 32-byte page write buffer and supports
both the Standard (100kHz) as well as Fast (400kHz)
I
2
C protocol.
External address pins make it possible to address up
to eight CAT24C32 devices on the same bus.
PIN CONFIGURATION
PDIP (L), SOIC (W), TSSOP (Y)
TDFN (VP2), UDFN (HU3)
A
0
A
1
A
2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
FUNCTIONAL SYMBOL
V
CC
SCL
A
2
, A
1
, A
0
WP
CAT24C32
SDA
Note:
For the location of Pin 1, please consult the corresponding
package drawing.
PIN FUNCTIONS
Name
A
0
, A
1
, A
2
SDA
SCL
WP
V
CC
V
SS
Description
Device Address
Serial Data
Serial Clock
Write Protect
Power Supply
Ground
Notes:
* Catalyst carries the I
2
C protocol under a license from the Philips
Corporation.
** The Green & Gold seal identifies RoHS-compliant packaging,
using NiPdAu pre-plated lead frames.
V
SS
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
1
Doc. No.
MD-1101,
Rev. K
CAT24C32
ABSOLUTE MAXIMUM RATINGS
(1)
Storage Temperature
Voltage on any pin with respect to Ground
(2)
RELIABILITY CHARACTERISTICS
(3)
Symbol
N
END(4)
T
DR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/Erase Cycles
Years
-65°C to +150°C
-0.5V to +6.5V
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.8V to 5.5V, T
A
= -40°C to +125°C and V
CC
= 1.7V to 5.5V, T
A
= -20°C to +85°C, unless otherwise specified.
Symbol Parameter
I
CCR
I
CCW
I
SB
Read Current
Write Current
Standby Current
Test Conditions
Read, f
SCL
= 400kHz
Write, f
SCL
= 400kHz
All I/O Pins at GND or V
CC
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
I
L
V
IL
V
IH
V
OL1
V
OL2
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage V
CC
< 2.5V, I
OL
= 3.0mA
Output Low Voltage V
CC
< 2.5V, I
OL
= 1.0mA
Pin at GND or V
CC
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
-0.5
V
CC
x 0.7
Min
Max
1
2
1
2
1
2
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.2
V
V
V
V
µA
Units
mA
mA
µA
PIN IMPEDANCE CHARACTERISTICS
V
CC
= 1.8V to 5.5V, T
A
= -40°C to +125°C and V
CC
= 1.7V to 5.5V, T
A
= -20°C to +85°C, unless otherwise specified.
Symbol Parameter
C
IN
C
IN
I
WP
(3)
(3)
Conditions
V
IN
= 0V, T
A
= 25°C, f = 1.0MHz
V
IN
= 0V, T
A
= 25°C, f = 1.0MHz
V
IN
< V
IH
V
IN
> V
IH
Max
8
6
200
1
Units
pF
pF
µA
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current
(5)
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than V
CC
+ 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than V
CC
+ 1.5V, for periods of less than 20ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, V
CC
= 5V, 25°C.
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull-down reverts to a weak current source.
Doc. No.MD-1101, Rev.K
2
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT24C32
A.C. CHARACTERISTICS
(1)
V
CC
= 1.8V to 5.5V, T
A
= -40°C to +125°C and V
CC
= 1.7V to 5.5V, T
A
= -20°C to +85°C, unless otherwise specified.
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F(2)
t
SU:STO
t
BUF
t
AA
t
DH
T
i(2)
t
SU:WP
t
HD:WP
t
WR
t
PU(2, 3)
Parameter
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power-up to Ready Mode
0
2.5
5
1
100
100
0
2.5
5
1
4
4.7
3.5
100
100
4
4.7
4
4.7
0
250
1000
300
0.6
1.3
0.9
Standard
Min
Max
100
0.6
1.3
0.6
0.6
0
100
300
300
Min
Fast
Max
400
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
ns
ns
µs
µs
ms
ms
Units
A.C. TEST CONDITIONS
Input Drive Levels
Input Rise and Fall Time
Input Reference Levels
Output Reference Level
Output Test Load
0.2 x V
CC
to 0.8 x V
CC
≤
50ns
0.3 x V
CC
, 0.7 x V
CC
0.5 x V
CC
Current Source I
OL
= 3mA (V
CC
≥
2.5V); I
OL
= 1mA (V
CC
< 2.5V); C
L
= 100pF
Notes:
(1) Test conditions according to “A.C. Test Conditions” table.
(2)
(3)
Tested initially and after a design or process change that affects this parameter.
t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
3
Doc. No.MD-1101, Rev. K
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT24C32
POWER-ON RESET (POR)
Each CAT24C32 incorporates Power-On Reset (POR)
circuitry which protects the internal logic against
powering up in the wrong state. The device will power
up into Standby mode after V
CC
exceeds the POR
trigger level and will power down into Reset mode
when V
CC
drops below the POR trigger level. This bi-
directional POR behavior protects the device against
‘brown-out’ failure following a temporary loss of power.
FUNCTIONAL DESCRIPTION
The CAT24C32 supports the Inter-Integrated Circuit
(I
2
C) Bus protocol. The protocol relies on the use of a
Master device, which provides the clock and directs
bus traffic, and Slave devices which execute requests.
The CAT24C32 operates as a Slave device. Both
Master and Slave can transmit or receive, but only the
Master can assign those roles.
I C BUS PROTOCOL
The 2-wire I
2
C bus consists of two lines, SCL and
SDA, connected to the V
CC
supply via pull-up
resistors. The Master provides the clock to the SCL
line, and either the Master or the Slaves drive the
SDA line. A ‘0’ is transmitted by pulling a line LOW
and a ‘1’ by letting it stay HIGH. Data transfer may be
initiated only when the bus is not busy (see A.C.
Characteristics). During data transfer, SDA must
remain stable while SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a
START or STOP condition (Figure 1). The START
consists of a HIGH to LOW SDA transition, while SCL
is HIGH. Absent the START, a Slave will not respond
to the Master. The STOP completes all commands,
and consists of a LOW to HIGH SDA transition, while
SCL is HIGH.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8-bit Slave
address. For the CAT24C32, the first four bits of the
Slave address are set to 1010 (Ah); the next three
bits, A
2
, A
1
and A
0
, must match the logic state of the
similarly named input pins. The R/W bit tells the Slave
whether the Master intends to read (1) or write (0)
data (Figure 2).
Acknowledge
During the 9
th
clock cycle following every byte sent to
the bus, the transmitter releases the SDA line,
allowing the receiver to respond. The receiver then
either acknowledges (ACK) by pulling SDA LOW, or
does not acknowledge (NoACK) by letting SDA stay
HIGH (Figure 3). Bus timing is illustrated in Figure 4.
2
PIN DESCRIPTION
SCL:
The Serial Clock input pin accepts the clock
signal generated by the Master.
SDA:
The Serial Data I/O pin accepts input data and
delivers output data. In transmit mode, this pin is open
drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A
0
, A
1
and A
2
:
The Address inputs set the device
address that must be matched by the corresponding
Slave address bits. The Address inputs are hard-wired
HIGH or LOW allowing for up to eight devices to be
used (cascaded) on the same bus. When left floating,
these pins are pulled LOW internally.
WP:
When pulled HIGH, the Write Protect input pin
inhibits all write operations. When left floating, this pin
is pulled LOW internally.
Doc. No.MD-1101, Rev.K
4
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT24C32
Figure 1. Start/Stop Timing
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Slave Address Bits
1
0
1
0
A
2
A
1
A
0
R/W
DEVICE ADDRESS
Figure 3. Acknowledge Timing
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
8
9
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ tSU:DAT)
START
ACK DELAY (≤ tAA)
Figure 4. Bus Timing
t
F
t
LOW
SCL
t
SU:STA
t
HD:SDA
SDA IN
t
AA
SDA OUT
t
DH
t
BUF
t
HD:DAT
t
SU:DAT
t
SU:STO
t
HIGH
t
LOW
t
R
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
5
Doc. No.MD-1101, Rev. K
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