QUAD NON-PROGRAMMABLE
PCM CODEC
FEATURES
•
•
•
PRELIMINARY
IDT821024
DESCRIPTION
The IDT821024 is a single-chip, four channel PCM CODEC with on-
chip filters. The device provides analog-to-digital and digital-to-analog
conversions and supports both a-law and
µ−law
companding. The digital
filters in IDT821024 provides the necessary transmit and receive filtering
for voice telephone circuit to interface with time-division multiplexed
systems. All of the digital filters are performed in digital signal processors
operating from an internal clock, which is derived from MCLK. The fixed
filters set the transmit and receive gain and frequency response.
In the IDT821024 the PCM data is transmitted to and received from
the PCM highway in time slots determined by the individual Frame Sync
signals (FSR
n
and FSX
n
, where n = 1-4) at rates from 256 KHz to 8.192
MHz. Both Long and Short Frame Sync modes are available in the
IDT821024.
The IDT821024 can be used in digital telecommunication applications
such as PBX, Central Office Switch, Digital Telephone and Integrated Voice/
Data Access Unit.
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•
•
•
•
•
•
4 channel CODEC with on-chip digital filters
Selectable A-law or
µ-law
companding
Master clock frequency selection: 2.048 MHz, 4.096 MHz or
8.192 MHz
- Internal timing automatically adjusted based on MCLK and
frame sync signal
Separate PCM and master clocks
Single PCM port with up to 8.192 MHz data rate (128 time slots)
Transhybrid balance impedance hardware adjustable via external
components
Transmit gains hardware adjustable via external components
Low power +5.0 V CMOS technology
+5.0 V single power supply
Package available: PLCC_32_PL, TQFP_44_PF
FUNCTIONAL BLOCK DIAGRAM
IIN1
VOUT1
IIN2
VOUT2
IIN3
VOUT3
Anolog Front End
CH1
PCM TSA 1
PCM TSA 2
PCM TSA 3
PCM TSA 4
FSX1
FSR1
FSX2
FSR2
FSX3
FSR3
FSX4
FSR4
DX
TSC
DR
PCLK
Anolog Front End
CH2
DSP
Anolog Front End
CH3
IIN4
VOUT4
Anolog Front End
CH4
PCM Interface
MCLK
IREF
CNF
Clock
&
Reference Circuits
PDN 1~ 4
Control
A/µ
AGND
The IDT logo is a registered trademark of Integrated Device Technology, Inc
INDUSTRIAL TEMPERATURE RANGE
1
©2001
Integrated Device Technology, Inc.
DGND
VCCA
VCCD
MARCH 2002
DSC-6034/2
IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
VOUT1
MCLK
30
PDN1
PDN2
PDN3
32
PDN4
31
CNF
3
4
2
1
IIN1
IIN2
VOUT2
VCCA
IREF
AGND
VOUT3
IIN3
IIN4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
13
29
28
27
PCLK
TSC
DGND
DX
VCCD
DR
FSR1
FSX1
FSR2
32-Pin
PLCC
26
25
24
23
22
21
20
FSX2
MCLK
35
VOUT4
FSX4
FSR4
FSX3
VOUT1
FSR3
A/
µ
44
43
42
41
40
39
38
37
36
34
PCLK
PDN1
PDN2
PDN3
PDN4
CNF
IIN1
NC
NC
IIN2
VOUT2
NC
NC
VCCA
IREF
AGND
NC
NC
VOUT3
IIN3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
NC
NC
TSC
DGND
NC
DX
VCCD
DR
FSR1
FSX1
FSR2
44-Pin
TQFP
30
29
28
27
26
25
24
23
VOUT4
FSX4
FSX3
FSR4
2
FSR3
FSX2
NC
NC
IIN4
A/µ
NC
IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Name
AGND
VCCA
DGND
VCCD
DR
I/O
--
--
--
--
I
Pin Number
PLCC
TQFP
10
8
27
25
24
7
5
30
27
26
Description
Analog Ground.
All ground pins should be connected to the ground plane of the circuit board.
+5 V Analog Power Supply.
All power supply pins should be connected to the power plane of the circuit board.
Digital Ground.
All ground pins should be connected to the ground plane of the circuit board.
+5 V Digital Power Supply.
All power supply pins should be connected to the power plane of the circuit board.
Receive PCM Data Input.
The PCM data for Channel 1, 2, 3 and 4 is shifted serially into DR pin by the Receive Frame Sync Signal
(FSR) with MSB first. A byte of data for each channel is received every 125
µ
s at the PCLK rate.
Transmit PCM Data Output.
The PCM data for Channel 1, 2, 3 and 4 is shifted serially out to the DX pin by the Transmit Frame Sync Signal
(FSX) with MSB first. A byte of data for each channel is transmitted every 125
µ
s at the PCLK rate. DX is high
impedance between time slots.
Receive Frame Sync Input for Channel 1/2/3/4
This 8kHz signal pulse identifies the receive time slot for Channel N on a system’s receive PCM frame. It must
be synchronized to PCLK.
Transmit Frame Sync Input for Channel 1/2/3/4
This 8 kHz signal pulse identifies the transmit time slot for Channel N on a system’s transmit PCM frame. It
must be synchronized to PCLK.
Reference Current.
The IREF output is biased at the internal reference voltage. A resistor placed from IREF to ground sets the
reference current used by the analog-to-digital converter to encode the signal current present on IINn pin (n is
channel number, n = 1 to 4) into digital form.
Voice Frequency Receiver Output for Channel 1/2/3/4
This is the output of receiver amplifier for Channel N. The received digital data from DR is processed and
converted to an analog signal at this pin.
Voice Frequency Transmitter Input for Channel 1/2/3/4
This is the input to the gain setting amplifier in the transmit path for Channel N. The analog voice band voltage
signal is applied to this pin through a resistor. This input is a virtual AC ground input, which is biased at the
IREF pin.
Master Clock.
The Master Clock provides the clock for the DSP. It can be either 2.048 MHz or 4.096 MHz. The IDT821024
determines the MCLK frequency via the FSX inputs and makes the necessary internal adjustments
automatically. The MCLK frequency must be an integer multiple of the FSX frequency.
PCM Clock.
The PCM Clock shifts out the PCM data to the DX pin and shifts in PCM data from the DR pin. The PCM clock
frequency is an integer multiple of the frame sync frequency. When PCLK is connected to MCLK, the PCM
clock can generate the DSP clock as well.
Time Slot Control.
This open drain output is low active. When the PCM data is transmitted to the DX pin for any of the four
channels, this pin will be pulled low.
A/
µ
-Law Selection.
When this pin is low,
µ
-Law is selected; when this pin is high, A-Law is selected. This pin can be connected to
VCCD or DGND pin directly.
DX
O
26
28
FSR1
FSR2
FSR3
FSR4
FSX1
FSX2
FSX3
FSX4
I
23
21
19
17
22
20
18
16
25
23
21
19
24
22
20
18
I
IREF
O
9
6
VOUT1
VOUT2
VOUT3
VOUT4
IIN1
IIN2
IIN3
IIN4
O
4
7
11
14
5
6
12
13
43
2
10
13
44
1
11
12
I
MCLK
I
30
35
PCLK
I
29
34
TSC
O
28
31
A/
µ
I
15
16
3
IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
(cont’d)
Name
PDN1
PDN2
PDN3
PDN4
CNF
I/O
Pin Number
PLCC
TQFP
2
1
32
31
3
39
38
37
36
41
3, 4, 8, 9,
14, 15, 17,
29, 32, 33,
40, 42
Description
Channel 1/2/3/4 Power Down.
When this pin is high, Channel N is powered down.
Capacitor For Noise Filter.
This pin should be connected to AGND through a 0.1
µ
F capacitor.
I
O
NC
--
No connection
4
IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
and compressed to PCM format.
Transmit PCM Interface
The transmit PCM interface clocks out 1 byte (8 bits) PCM data out of
DX pin every 125
µs.
The transmit logic, synchronized by the Transmit
Frame Sync signal (FSXn), controls the data transmission. The FSXn
pulse identifies the transmit time slot of the PCM frame for Channel N.
The PCM Data is transmitted serially on DX pin with the Most Significant
Bit (MSB) first. When the PCM data is being output on DX pin, the
TSC
signal will be pulled low.
Receive Signal Processing
In the receive path, the PCM code is received at the rate of 8,000 samples
per second. The PCM code is expanded and sent to the DSP for
interpolation. A receive filter is implemented in the DSP as a digital lowpass
filter. The filtered signal is then sent to an oversampling DAC. The DAC
output is post-filtered and delivered at VOUT pin by an amplifier. The
amplifier can drive resistive load higher than 2 KΩ.
Receive PCM Interface
The receive PCM interface clocks 1 byte (8 bits) PCM data into DR pin
every 125
µs.
The receive logic, synchronized by the Receive Frame Sync
signal (FSRn), controls the data receiving process. The FSRn pulse
identifies the receive time slot of the PCM frame for Channel N. The PCM
Data is received serially on DR pin with the Most Significant Bit (MSB)
first.
Hardware Gain Setting In Transmit Path
The transmit gain of the IDT821024 for each channel can be set by 2
resistors, R
REF
and R
TXn
(as shown in Figure 1), according to the follow-
ing equation:
G
t
=
3
×
R
REF
R
TXn
The IDT821024 contains four channel PCM CODEC with on chip digital
filters. It provides the four-wire solution for the subscriber line circuitry in
digital switches. The device converts analog voice signal to digital PCM
data, and converts digital PCM data back to analog signal. Digital filters
are used to bandlimit the voice signals during the conversion. Either A-law
or
µ-law
is supported by the IDT821024. The law selection is performed
by A/µ pin.
The frequency of the master clock (MCLK) can be 2.048 MHz, 4.096
MHz, or 8.192 MHz. Internal circuitry determines the master clock frequency
automatically.
The serial PCM data for four channels are time multiplexed via two pins,
DX and DR. The time slots of the four channels are determined by the
individual Frame Sync signals at rates from 256 kHz to 8.192 MHz. For
each channel, the IDT821024 provides a transmit Frame Sync signal and
a receive Frame Sync signal.
Each channel of the IDT821024 can be powered down independently
to save power consumption. The Channel Power Down Pins PDN1-4
configure channels to be active (power-on) or standby (power-down)
separately.
Signal Processing
High performance oversampling Analog-to-Digital Converters (ADC) and
Digital-to-Analog Converters (DAC) are used in the IDT821024 to provide
the required conversion accuracy. The associated decimation and interpo-
lation filtering are realized with both dedicated hardware and Digital Signal
Processor (DSP). The DSP also handles all other necessary functions such
as PCM bandpass filtering and sample rate conversion.
Transmit Signal Processing
In the transmit path, the analog input signal is received by the ADC and
converted into digital data. The digital output of the oversampling ADC is
decimated and sent to the DSP. The transmit filter is implemented in the
DSP as a digital bandpass filter. The filtered signal is further decimated
The receive gain of IDT821024 is fixed and equal to 1.
to
SLIC
VTX
IDT821024
R
TX
1
C
TX
1
V
IN
1
A/D
I
REF
Bal
Net
V
REF
to
I
REF
I
REF
1
V
REF
1
R
REF
1
C
FIL
to
SLIC
RSN
R
RX
1
C
RX
1
V
OUT
1
V
REF
D/A
Figure 1. IDT821024 Transmit Gain Setting for Channel 1
5
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