IDT74LVC16241A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT
BUFFER/DRIVER WITH 3-STATE
OUTPUTS, 5 VOLT TOLERANT I/O
FEATURES:
Typical
t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP
and 0.40mm pitch TVSOP packages
– Extended commercial range of -40°C to +85°C
– V
CC
= 3.3V ±0.3V, Normal Range
– V
CC
= 2.7V to 3.6V, Extended Range
– CMOS power levels (0.4µ W typ. static)
– All inputs, outputs and I/O are 5 Volt tolerant
– Supports hot insertion
Drive Features for LVC16241A:
– High Output Drivers: ±24mA
– Reduced system switching noise
–
–
IDT74LVC16241A
DESCRIPTION:
This 16-bit buffer/driver is built using advanced dual metal CMOS
technology.The LVC16241A is designed specifically to improve both the
performance and density of 3-state memory address drivers, clock drivers,
and bus-oriented receivers and transmitters. This device can be used as
four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer, and provides true
outputs and complementary output-enable (OE and
OE)
inputs.
To ensure the high impedance state during power up or power down,
OE
should be tied to V
CC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking capability of the driver. OE
should be tied to GND through a pulldown resistor; the minimum value of
the resistor is determined by the current-sourcing capability of the driver.
All pins of this 16-bit buffer/driver can be driven from either 3.3V or 5V
devices. This feature allows the use of this device as a translator in a mixed
3.3V/5V supply system.
The LVC16241A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
Functional Block Diagram
1
OE
1
3
OE
25
1
A
1
47
2
1
Y
1
3
A
1
36
13
3
Y
1
46
1
A
2
3
1
Y
2
3
A
2
35
14
3
Y
2
1
A
3
44
5
1
Y
3
3
A
3
33
16
3
Y
3
43
1
A
4
6
32
1
Y
4
3
A
4
17
3
Y
4
2
OE
48
4
OE
24
2
A
1
41
8
2
Y
1
4
A
1
30
19
4
Y
1
40
2
A
2
9
2
Y
2
4
A
2
29
20
4
Y
2
2
A
3
38
11
2
Y
3
4
A
3
27
22
4
Y
3
37
2
A
4
12
2
Y
4
4
A
4
26
23
4
Y
4
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
MAY 1999
DSC-4555/1
IDT74LVC16241A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM(2)
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through
each V
CC
or GND
(1)
Unit
V
V
°C
mA
mA
mA
LVC Link
Max.
– 0.5 to +6.5
– 0.5 to +6.5
– 65 to +150
– 50 to +50
– 50
±100
1
O E
1
Y
1
1
Y
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
SO48-1
SO48-2 37
SO48-3
36
35
34
33
32
31
30
29
28
27
26
25
2
O E
1
A
1
1
A
2
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
G ND
1
Y
3
1
Y
4
G ND
1
A
3
1
A
4
V
CC
2
Y
1
2
Y
2
V
CC
2
A
1
2
A
2
G ND
2
Y
3
2
Y
4
3
Y
1
3
Y
2
G ND
2
A
3
2
A
4
3
A
1
3
A
2
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
G ND
3
Y
3
3
Y
4
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
6.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
LVC Link
G ND
3
A
3
3
A
4
V
CC
4
Y
1
4
Y
2
V
CC
4
A
1
4
A
2
G ND
4
Y
3
4
Y
4
4
O E
G ND
4
A
3
4
A
4
3
O E
NOTE:
1. As applicable to the device type.
FUNCTION TABLES
(1)
Inputs
1OE, 4OE
1Ax, 4Ax
H
L
X
L
L
H
Outputs
1Yx, 4Yx
H
SSOP/ TSSOP/ TVSOP
TOP VIEW
L
Z
PIN DESCRIPTION
Pin Names
xOE
xOE
xAx
xYx
Description
3–State Output Enable Inputs (Active LOW)
3–State Output Enable Inputs
Data Inputs
3-State Outputs
Inputs
2OE, 3OE
H
H
L
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
2Ax, 3Ax
H
L
X
Outputs
2Yx, 3Yx
H
L
Z
c 1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74LVC16241A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40
O
C to +85
O
C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input Leakage Current
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤
5.5V
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
3.6
≤
V
IN
≤
5.5V
(2)
Quiescent Power Supply
Current Variation
One input at V
CC
- 0.6V
other inputs at V
CC
or GND
—
—
—
—
—
—
—
– 0.7
100
—
—
—
±50
– 1.2
—
10
10
500
µA
LVC Link
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= 0 to 5.5V
V
O
= 0 to 5.5V
Min.
1.7
2
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
Max.
—
—
0.7
0.8
±5
±10
Unit
V
V
µA
µA
µA
V
mV
µA
NOTES:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2.2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
LVC Link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to +85°C.
3
IDT74LVC16241A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, VCC = 3.3V
±
0.3V, TA = 25°C
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance per buffer/driver Outputs enabled
Power Dissipation Capacitance per buffer/driver Outputs disabled
(1)
V
CC
= 2.7V
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SK
(o)
Parameter
Propagation Delay
xAx to xYx
Output Enable Time
1
OE
to
1
Yx,
4
OE
to
4
Yx
Output Disable Time
1
OE
to
1
Yx,
4
OE
to
4
Yx
Output Enable Time
2
OE to
2
Yx,
3
OE to
3
Yx
Output Disable Time
2
OE to
2
Yx,
3
OE to
3
Yx
Output Skew
(2)
Min.
1.5
1.5
1.5
1.5
1.5
Max.
6
7.1
6.8
7.5
7.3
V
CC
= 3.3V±0.3V
Min.
1.5
1.5
1.5
1.5
1.5
Max.
5
6.1
5.8
6.5
6.3
500
Unit
ns
ns
ns
ns
ns
ps
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
Unit
pF
pF
SWITCHING CHARACTERISTICS
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC16241A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS:
TEST CONDITIONS
PROPAGATION DELAY
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 3.3V ±0.3V
6
2.7
1.5
300
300
50
V
CC
(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
(2)
= 2.5V ±0.2V Unit
2 x Vcc
V
Vcc
V
CC
/ 2
150
150
30
V
V
mV
mV
pF
LVC Link
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
LVC Link
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
Pulse
(1, 2)
Generator
V
IN
D.U.T.
500
Ω
C
L
V
OUT
V
LOAD
Open
GND
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SW ITCH
NORMALLY
CLOSED
LOW
t
PZH
OUTPUT
SW ITCH
NORMALLY
OPEN
HIGH
V
LOAD/2
V
T
t
PHZ
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD/2
V
OL+
V
LZ
V
OL
V
OH
V
OH-
V
HZ
0V
R
T
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
LVC Link
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
LVC Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
LVC Link
t
SU
t
H
GND
Open
t
REM
OUTPUT SKEW - tsk (x)
V
IH
INPUT
V
T
0V
V
OH
OUTPUT 1
V
T
V
OL
V
OH
OUTPUT 2
t
PLH2
t
PHL2
V
T
V
OL
SYNCHRONOUS
CONTROL
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
LVC Link
t
PLH1
t
PHL1
PULSE WIDTH
LOW -HIGH-LOW
PULSE
t
W
HIGH-LOW -HIGH
PULSE
V
T
LVC Link
V
T
t
SK
(x)
t
SK
(x)
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
LVC
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
Link
5
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