BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
128K X 8 bit
DESCRIPTION
BS62LV1024
• Easy expansion with CE2, CE1, and OE options
The BS62LV1024 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.02uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV1024 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV1024 is available in JEDEC standard 32 pin 450mil Plastic
SOP, 300mil Plastic SOJ , 600mil Plastic DIP, 8mmx13.4mm STSOP,
8mmx13.4mm Reverse STSOP and 8mmx20mm TSOP.
SPEED
(n s )
V cc=3V
P O W E R D IS S IP AT IO N
S ta n d b y
O p e r a tin g
(Ic c , M a x )
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.02uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
PRODUCT FAMILY
PRODUCT
F A M ILY
B S 6 2 LV 1 0 2 4 S C
B S 6 2 LV 1 0 2 4 T C
B S 6 2 LV 1 0 2 4 S T C
B S 6 2 LV 1 0 2 4 P C
B S 6 2 LV 1 0 2 4 J C
B S 6 2 LV 1 0 2 4 R C
B S 6 2 LV 1 0 2 4 S I
B S 6 2 LV 1 0 2 4 T I
B S 6 2 LV 1 0 2 4 S T I
B S 6 2 LV 1 0 2 4 P I
B S 6 2 LV 1 0 2 4 J I
B S 6 2 LV 1 0 2 4 R I
O P E R AT IN G
T E M P E R AT U R E
Vcc
RANGE
(
Ic c S B 1 , M a x )
V cc=5V V cc=3V
PKG TYPE
S O P -3 2
T S O P -3 2
S T S O P -3 2
P D IP -3 2
S O J -3 2
R e ve rs e
S T S O P -3 2
S O P -3 2
T S O P -3 2
S T S O P -3 2
P D IP -3 2
S O J -3 2
R e ve rs e
S T S O P -3 2
V cc=5V
V cc=3V
0
O
C to + 7 0
O
C
2 .4 V ~ 5 .5 V
70
3 .0 u A
1 .0 u A
35m A
20m A
-4 0
O
C to + 8 5
O
C
2 .4 V ~ 5 .5 V
70
5 .0 u A
1 .5 u A
40m A
25m A
PIN CONFIGURATIONS
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
BLOCK DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
Brilliance Semiconductor, Inc
.
reserves the right to modify document contents without notice.
R0201-BS62LV1024
•
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
BS62LV1024SC
27
BS62LV1024SI
26
BS62LV1024PC
25
BS62LV1024PI
24
BS62LV1024JC
BS62LV1024JI
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
•
BS62LV1024TC
BS62LV1024STC
BS62LV1024TI
BS62LV1024STI
A6
A7
A12
A14
A16
A15
A13
A8
A9
A11
Address
Input
Buffer
20
Row
Decoder
1024
Memory Array
1024 x 1024
1024
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
128
Column Decoder
14
Control
Address Input Buffer
8
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BS62LV1024RC
BS62LV1024RI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
Data
Output
Buffer
8
•
CE2
CE1
WE
OE
Vdd
Gnd
A5 A4 A3 A2 A1 A0 A10
1
Revision 2.4
Jan.
2004
BSI
PIN DESCRIPTIONS
BS62LV1024
Function
These 17 address inputs select one of the 131,072 x 8-bit words in the RAM
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
Name
A0-A16 Address Input
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
DQ0-DQ7 Data Input/Output
Ports
Vcc
Gnd
TRUTH TABLE
MODE
WE
CE1
CE2
OE
I/O OPERATION
Vcc CURRENT
Not selected
(Power Down)
Output Disabled
Read
Write
X
X
H
H
L
H
X
L
L
L
X
L
H
H
H
X
X
H
L
X
High Z
High Z
D
OUT
D
IN
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
OPERATING RANGE
UNITS
V
O
RATING
-0.5 to
Vcc+0.5
-40 to +85
-60 to +150
1.0
20
RANGE
Commercial
Industrial
AMBIENT
TEMPERATURE
0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
2.4V ~ 5.5V
2.4V ~ 5.5V
C
C
O
W
mA
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
C
IN
C
DQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
V
IN
=0V
V
I/O
=0V
6
8
pF
pF
1. This parameter is guaranteed and not 100% tested.
R0201-BS62LV1024
2
Revision 2.4
Jan.
2004
BSI
DC ELECTRICAL CHARACTERISTICS
( TA = 0
o
C to + 70
o
C )
PARAMETER
NAME
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
I
CCSB
I
CCSB1
BS62LV1024
TEST CONDITIONS
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
PARAMETER
Guaranteed Input Low
Voltage
(2)
Guaranteed Input High
Voltage
(2)
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Standby Current-TTL
Standby Current-CMOS
MIN. TYP.
(1)
MAX.
-0.5
2.0
2.2
--
--
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
UNITS
V
V
uA
uA
V
V
mA
mA
uA
--
--
--
--
--
--
--
--
--
--
0.02
0.4
0.8
Vcc+0.2
1
1
0.4
--
20
35
1
2
1
3
Vcc = Max, V
IN
= 0V to Vcc
Vcc = Max, CE1= V
IH
, CE2= V
IL,
or
OE = V
IH
, V
I/O
= 0V to Vcc
Vcc = Max, I
OL
= 2mA
Vcc = Min, I
OH
= -1mA
CE1 = V
IL
, or CE2 = V
IH
,
I
DQ
= 0mA, F = Fmax
(3)
CE1 = V
IH
, or CE2 = V
IL
,
I
DQ
= 0mA
CE1≧Vcc-0.2V or CE2≦0.2V,
V
IN
≧Vcc-0.2V
or V
IN
≦0.2V
--
2.4
--
--
--
--
--
--
1. Typical characteristics are at TA = 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
RC
.
DATA RETENTION CHARACTERISTICS
( TA = 0
o
C to + 70
o
C )
SYMBOL
V
DR
I
CCDR
t
CDR
t
R
PARAMETER
Vcc for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
TEST CONDITIONS
CE1
≧
Vcc - 0.2V or CE2
≦
0.2V,
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
CE1
≧
Vcc - 0.2V or CE2
≦
0.2V,
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
See Retention Waveform
MIN.
1.5
--
0
T
RC (2)
TYP.
(1)
--
0.02
--
--
MAX.
--
0.3
--
--
UNITS
V
uA
ns
ns
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
LOW V
CC
DATA RETENTION WAVEFORM (1)
( CE1 Controlled )
Data Retention Mode
V
DR
≥
1.5V
Vcc
V
IH
Vcc
Vcc
t
CDR
CE1
≥
Vcc - 0.2V
t
R
V
IH
CE1
LOW V
CC
DATA RETENTION WAVEFORM (2)
( CE2 Controlled )
Data Retention Mode
Vcc
Vcc
V
DR
≧
1.5V
Vcc
t
CDR
t
R
CE2
≦
0.2V
CE2
R0201-BS62LV1024
V
IL
V
IL
3
Revision 2.4
Jan.
2004
BSI
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
1V/ns
0.5Vcc
WAVEFORM
INPUTS
BS62LV1024
KEY TO SWITCHING WAVEFORMS
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
AC TEST LOADS AND WAVEFORMS
3.3V
OUTPUT
100PF
INCLUDING
JIG AND
SCOPE
1269
Ω
3.3V
OUTPUT
1269
Ω
,
5PF
1404
Ω
INCLUDING
JIG AND
SCOPE
1404
Ω
FIGURE 1A
THEVENIN EQUIVALENT
667
Ω
FIGURE 1B
OUTPUT
1.73V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
←
→
←
5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS
( TA = 0
o
C to + 70
o
C, Vcc=3.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Output Disable to Address Change
(CE1)
(CE2)
(CE1)
(CE2)
(CE1)
(CE2)
CYCLE TIME : 70ns
MIN. TYP. MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AVAX
t
AVQV
t
E1LQV
t
E2HOV
t
GLQV
t
E1LQX
t
E2HOX
t
GLQX
t
E1HQZ
t
E2HQZ
t
GHQZ
t
AXOX
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
CLZ1
t
CLZ2
t
OLZ
t
CHZ1
t
CHZ2
t
OHZ
t
OH
70
--
--
--
--
10
10
10
0
0
0
10
--
--
--
--
--
--
--
--
--
--
--
--
70
70
70
50
--
--
--
40
40
35
--
R0201-BS62LV1024
4
Revision 2.4
Jan.
2004
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
BS62LV1024
t
RC
ADDRESS
t
D
OUT
t
OH
AA
t
OH
READ CYCLE2
CE1
(1,3,4)
t
CE2
(5)
CLZ
ACS1
t
t
ACS2
t
CHZ1,
t
(5)
CHZ2
D
OUT
(1,4)
READ CYCLE3
t
RC
ADDRESS
t
OE
AA
t
CE1
OE
t
OH
t
t
(5)
CLZ1
OLZ
t
ACS1
t
OHZ
(5)
(1,5)
t
CHZ1
CE2
t
t
(5)
CLZ2
ACS2
t
(2,5)
CHZ2
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
IL
and CE2= V
IH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = V
IL
.
5. Transition is measured
±
500mV from steady state with C
L
= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
R0201-BS62LV1024
5
Revision 2.4
Jan.
2004
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
