SPT7750
8-BIT, 500 MSPS, FLASH A/D CONVERTER
TECHNICAL DATA
FEATURES
•
•
•
•
•
•
1:2 Demuxed ECL compatible outputs
Wide input bandwidth – 900 MHz
Low input capacitance – 15 pF
Metastable errors reduced to 1 LSB
Monolithic for low cost
Gray code output
APPLICATIONS
•
•
•
•
Digital oscilloscopes
Transient capture
Radar, EW, ECM
Direct RF down-conversion
NOVEMBER 30, 2001
GENERAL DESCRIPTION
The SPT7750 is a full parallel (flash) analog-to-digital con-
verter capable of digitizing full scale (0 to –2 V) inputs into
eight-bit digital words at an update rate of 500 MSPS. The
ECL-compatible outputs are demultiplexed into two sepa-
rate output banks, each with differential data ready out-
puts to ease the task of data capture. The SPT7750’s wide
input bandwidth and low capacitance eliminate the need
for external track-and-hold amplifiers for most applica-
tions. A proprietary decoding scheme reduces metastable
errors to the 1 LSB level. The SPT7750 operates from a
single –5.2 V supply, with a nominal power dissipation of
5.5 W.
The SPT7750 is available in an 80-lead surface-mount
MQuad package over the industrial temperature range
(–25 °C to +85 °C) and in die form.
BLOCK DIAGRAM
V
RT
Analog
Input
Preamp
Comparator
256
CLK CLK
CLOCK
BUFFER
DEMUX
CLOCK
BUFFER
255
D8
(OVR)
D7
(MSB)
D6
DRB (DATA READY)
D8B
D7B
D6B
D5B
D4B
D3B
D2B
DRB (DATA READY)
D8B (OVR)
D7B (MSB)
D5B
D6B
152
256 TO 8 Bit Decoder
With Metastable Error Correction
ECL Output Buffers And Latches
151
D4B
D3B
D2B
D1B
D0B (LSB)
DRA (DATA READY)
DRA (DATA READY)
D8A (OVR)
D7A (MSB)
D5A
D4A
D3A
D2A
D1A
D0A (LSB)
D6A
1:2 DEMULTIPLEXER
128
D5
D1B
D0B
V
RM
127
D4
D8A
D7A
D6A
D5A
D4A
D3A
D2A
D1A
D0A
64
D3
63
D2
2
D1
1
D0
(LSB)
V
RB
BANK A
BANK B
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25 °C
Supply Voltages
Negative Supply Voltage (V
EE
TO GND) –7.0 to +0.5 V
Ground Voltage Differential .................... –0.5 to +0.5 V
Input Voltage
Analog Input Voltage ............................... +0.5 V to V
EE
Reference Input Voltage .......................... +0.5 V to V
EE
Digital Input Voltage ................................ +0.5 V to V
EE
Reference Current V
RT
to V
RB
........................... 35 mA
Output
Digital Output Current ............................... 0 to –28 mA
Temperature
Operating Temperature, ambient ............ –25 to +85 °C
case .......................... +125 °C
junction ..................... +150 °C
Lead Temperature, (soldering 10 seconds) ..... +300 °C
Storage Temperature ............................ –65 to +150 °C
Note:
1. Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
T
J
= T
C
= T
A
= +25 °C , V
EE
=–5.2 V, V
RB
=–2.0 V, V
RM
=–1.0 V, V
RT
=0.00 V, ƒ
CLK
=500 MHz, Duty Cycle=50%, unless otherwise specified.
PARAMETERS
Resolution
DC Accuracy
Integral Linearity Error (ILE)
Differential Linearity Error
(DLE)
No Missing Codes
Analog Input
Input Voltage Range
Input Bias Current
Input Resistance
Input Capacitance
Input Bandwidth
Small Signal
Large Signal
Offset Error V
RT
Offset Error V
RB
Input Slew Rate
Clock Synchronous
Input Currents
Reference Input
Ladder Resistance
Reference Bandwidth
Timing Characteristics
Maximum Sample Rate
Aperture Jitter
Acquisition Time
CLK to Data Ready Delay
Clock to Data Delay
Dynamic Performance
Signal-To-Noise Ratio
(without Harmonics)
ƒ
IN
= 50 MHz
ƒ
IN
= 250 MHz
Total Harmonic Distortion
ƒ
IN
= 50 MHz
ƒ
IN
= 250 MHz
Signal-to-Noise and Distortion
ƒ
IN
= 50 MHz
ƒ
IN
= 250 MHz
TEST
CONDITIONS
TEST
LEVEL
SPT7750A
MIN
TYP
MAX
8
SPT7750B
MIN
TYP
MAX UNITS
8
Bits
+1.5
+1.5
Guaranteed
LSB
LSB
ƒ
CLK
= 100 kHz
ƒ
CLK
= 100 kHz
I
I
–1.0
–0.85
Guaranteed
+1.0
+0.95
–1.5
–0.95
V
IN
=0 V
Over Full Input Range
I
I
V
V
V
V
IV
IV
V
V
I
V
I
V
V
IV
IV
V
RB
.75
15
15
900
500
–30
–30
5
2
60
80
30
V
RT
2.0
V
RB
.75
15
15
900
500
V
RT
2.0
V
mA
kΩ
pF
MHz
MHz
mV
mV
V/ns
µA
Ω
MHz
MHz
ps
ps
ns
ns
+30
+30
–30
–30
5
2
60
80
30
+30
+30
500
0.9
1.25
2
250
1.4
1.75
1.9
2.25
500
0.9
1.25
2
250
1.4
1.75
1.9
2.25
I
I
I
I
I
I
47
44
–46
–38
43
37
45
42
–44
–36
41
35
dB
dB
dBc
dBc
dB
dB
SPT7750
2
11/30/01
ELECTRICAL SPECIFICATIONS
T
J
= T
C
= T
A
= +25 °C , V
EE
=–5.2 V, V
RB
=–2.0 V, V
RM
=–1.0 V, V
RT
=0.00 V, ƒ
CLK
=500 MHz, Duty Cycle=50%, unless otherwise specified.
PARAMETERS
Dynamic Performance
Spurious Free Dynamic Range
ƒ
IN
= 50 MHz
ƒ
IN
= 250 MHz
Digital Inputs
Input High Voltage
(CLK,
CLK
)
Input Low Voltage
(CLK,
CLK
)
Clock Pulse Width High (t
PWH
)
Clock Pulse Width Low (t
PWL
)
Digital Outputs
Logic 1 Voltage
Logic 0 Voltage
Rise Time
Fall Time
Power Supply Requirements
Voltage V
EE
Current I
EE
Power Dissipation
TEST
CONDITIONS
TEST
LEVEL
SPT7750A
MIN
TYP
MAX
SPT7750B
MIN
TYP
MAX UNITS
I
I
49
41
44
36
dB
dB
I
I
I
I
I
I
V
V
IV
I
I
–1.1
1.0
1.0
–1.1
–0.7
–1.8
0.67
0.67
–0.9
–1.8
450
450
–5.2
1.05
5.5
–1.5
–1.1
1.0
1.0
–1.1
–1.5
–0.7
–1.8
0.67
0.67
–0.9
–1.8
450
450
–5.2
1.05
5.5
–1.5
V
V
ns
ns
V
V
ps
ps
–1.5
20% to 80%
20% to 80%
–4.95
–5.45
1.2
6.25
–4.95
–5.45 V
1.2 A
6.25 W
Typical Thermal Impedance:
θ
JC
= +4 °C/W.
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
Unless otherwise noted, all test are pulsed
tests; therefore, T
J
= T
C
= T
A
.
LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
= +25 °C, and sample tested at the
specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characteri-
zation data.
Parameter is a typical value for information purposes only.
100% production tested at T
A
= +25 °C. Parameter is guaranteed
over specified temperature range.
SPT7750
3
11/30/01
GENERAL DESCRIPTION
The SPT7750 is one of the fastest monolithic 8-bit parallel
flash A/D converters available today. The nominal conver-
sion rate is 500 MSPS and the analog bandwidth is in
excess of 900 MHz. A major advance over previous flash
converters is the inclusion of 256 input preamplifiers
between the reference ladder and input comparators (see
block diagram). This not only reduces clock transient kick-
back to the input and reference ladder due to a low AC
beta, but also reduces the effect of the dynamic state of
the input signal on the latching characteristics of the input
comparators. The preamplifiers act as buffers and stabi-
lize the input capacitance so that it remains constant over
different input voltage and frequency ranges and therefore
Figure 1 – SPT7750 Typical Interface Circuit
DRB
V
IN
**
50
W
V
IN
V
IN
DRB
DRA
makes the part easier to drive than previous flash convert-
ers. The preamplifiers also add a gain of two to the input
signal so that each comparator has a wider overdrive or
threshold range to “trip” into or out of the active state. This
gain reduces metastable states that can cause errors at
the output.
The SPT7750 has true differential analog and digital data
paths from the preamplifiers to the output buffers (Current
Mode Logic) for reducing potential missing codes while
rejecting common mode noise.
Signature errors are also reduced by careful layout of the
analog circuitry. The output drive capability of the device
can provide full ECL swings into 50
Ω
loads.
U3
DRB (DATA READY)
DRB (DATA READY)
DRA (DATA READY)
50
W
50
W
DRA
U3
DRA (DATA READY)
2.0 V Pulldown (Digital)
V
RTF
R
22
W
V
RTS
D8B (OVR)
D7B (MSB)
D6B
D5B
D4B
D3B
D2B
D1B
D0B (LSB)
D8A (OVR)
D7A (MSB)
D6A
D5A
D4A
D3A
D2A
D1A
D0A (LSB)
+
U1
R
*
V
RM
Convert
U2
CLK
CLK
50
W
50
W
AGND
DGND
50
W
50
W
V
EE
+
2.0 V
Reference
22
W
2N2907
U1
V
RBS
V
RBF
*
5.2 V
5.2 V
.1 µF
FB = Ferrite bead
2.0 V
Pulldown
(Digital)
2 V
Pulldown
(Analog)
U1 = OP291 or equivalent with low offset/noise.
R = 1 kW; 0.1% matched.
= AGND
= DGND
U2 = ON Semiconductor ECLinPS LITE, MC10EL16,
differential receiver with 250 ps (typ) propagation delay.
U3 = MC10EL16 or MC100EL16.
*
= 10 µF Tantalum Capacitor and 0.1 µF Chip Capacitor
*
5.2 V
FB
** = Care must be taken to avoid exceeding the maximum rating
for the input, especially during power up sequencing of the
analog input driver.
SPT7750
4
11/30/01
TYPICAL INTERFACE CIRCUIT
The circuit in figure 1 is intended to show the most elabo-
rate method of achieving the least error by correcting for
integral linearity, input induced distortion, and power sup-
ply/ground noise. This is achieved by the use of external
reference ladder tap connections, input buffer, and supply
decoupling. Please contact the factory for the SPT7750
evaluation board application note that contains more
details on interfacing the SPT7750. The function of each
pin and external connections to other components is as
follows:
V
EE
, AGND, DGND
V
EE
is the supply pin with AGND as ground for the device.
The power supply pins should be bypassed as close to the
device as possible with at least a .01 µF ceramic capaci-
tor. A 10 µF tantalum can also be used for low frequency
suppression. DGND is the ground for the ECL outputs and
is to be referenced to the output pulldown voltage and ap-
propriately bypassed as shown in figure 1.
V
IN
(ANALOG INPUT)
There are two analog input pins that are tied to the same
point internally. Either one may be used as an analog input
sense and the other for input force. This is convenient for
testing the source signal to see if there is sufficient drive
capability. The pins can also be tied together and driven by
the same source. The SPT7750 is superior to similar de-
vices due to a preamplifier stage before the comparators.
This makes the device easier to drive because it has con-
stant capacitance and induces less slew rate distortion.
CLK,
CLK
(CLOCK INPUTS)
The clock inputs are designed to be driven differentially
with ECL levels. The duty cycle of the clock should be kept
at 50% to avoid causing larger second harmonics. If this is
not important to the intended application, then duty cycles
other than 50% may be used.
D0 TO D8, DR,
DR
, (A AND B)
The digital outputs can drive 50
Ω
to ECL levels when
pulled down to –2 V. When pulled down to –5.2 V, the out-
puts can drive 130
Ω
to 1 kΩ loads. All digital outputs are
grey code with the coding as shown in table I. Fairchild rec-
ommends using differential receivers on the outputs of the
data ready lines to ensure the proper output rise and fall
times.
V
RBF
, V
RBS
, V
RTF
, V
RTS
, V
RM
(REFERENCE INPUTS)
There are two reference inputs and one external reference
voltage tap. These are –2 V (V
RB
force and sense), mid-
tap (V
RM
) and AGND (V
RT
force and sense). The refer-
ence pins and tap can be driven by op amps as shown in
figure 1 or V
RM
may be bypassed for limited temperature
operation. These voltage inputs can be bypassed to
AGND for further noise suppression if so desired.
Table I – Output Coding
V
IN
>–0.5 LSB
–0.5 LSB
–1.5 LSB
•
•
•
–1.0 V
•
•
•
–2.0 V +0.5 LSB
<(–2.0 V +0.5 LSB)
D8
1
1
0
0
0
•
•
•
0
0
•
•
•
0
0
0
D7 . . . D8
10000000
10000000
10000000
10000000
10000001
•
•
•
11000000
01000000
•
•
•
00000001
00000000
00000000
Indicates the transition between the two codes
THERMAL MANAGEMENT
The typical thermal impedance is as follows:
ΘCA
= +17 °C/W in still air with no heat sink
We highly recommend that a heat sink be used for this
device with adequate air flow to ensure rated performance
of the device. We have found that a Thermalloy 17846
heat sink with a minimum air flow of 1 meter/second (200
linear feet per minute) provides adequate thermal perfor-
mance under laboratory tests. Application specific condi-
tions should be taken into account to ensure that the
device is properly heat sinked.
SPT7750
5
11/30/01
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