DS2167/DS2168
DS2167/DS2168
ADPCM Processor
FEATURES
PIN ASSIGNMENT
RST
TM0
TM1
A0
A1
A2
A3
A4
A5
SPS
MCLK
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
YIN
CLKY
FSY
YOUT
CS
SDI
SCLK
XOUT
FSX
CLKX
XIN
•
Speech compression chip compatible with standard
ADPCM algorithms:
– DS2167 supports “new” T1Y1 recommenda-
tions (July 1986) and “new” CCITT G.721 rec-
ommendations
– DS2168 supports “old” CCITT G.721 recom-
mendations
•
Dual independent channel architecture – device may
be programmed to perform full duplex, 2-channel ex-
pansions, or 2-channel compressions
•
Interconnects directly with
µ-law
or A-law codec/filter
devices
24-Pin DIP (600 MIL)
CLKY
FSY
YOUT
CS
SDI
SCLK
XOUT
NC
TM1
TM0
RST
NC
VDD
YIN
NC
A0
A1
A2
A3
A4
A5
54 3 2
6
7
8
9
28-Pin PLCC
•
Serial PCM and control port interfaces minimize “glue
logic” in multiple channel applications
– On-chip channel counters identify input and out-
put timeslots in TDM-based systems
– Unique addressing scheme simplifies device
control; 3-wire port shared among 64 devices
– Bypass and idle features allow dynamic alloca-
tion of channel bandwidth, minimize system
power requirements
1 28 27 26 25
24
23
22
21
10
20
11
12 13 14 15 16 17 1819
SPS
MCLK
VSS
NC
XIN
CLKX
FSX
•
Hardware mode intended for stand-alone use
– No host processor required
– Ideal for voice mail applications
•
28-pin surface-mount package available, designated
DS2167Q/DS2168Q
DESCRIPTION
The DS2167 and DS2168 are dedicated digital signal
processor (DSP) CMOS chips optimized for Adaptive
Differential Pulse Code Modulation (ADPCM) based
compression algorithms. The devices halve the trans-
mission bandwidth of “toll quality” voice from 64K to 32K
bits/second and are utilized in PCM-based telephony
networks.
022698 1/15
DS2167/DS2168
PRODUCT OVERVIEW
The DS2167 and DS2168 contain three major function-
al blocks: a high performance (10 MIPS) DSP “engine,”
two independent PCM data interfaces (“X” and “Y”)
which connect directly to serial time division multiplexed
(TDM) backplanes and a microcontroller-compatible
serial port for on-the-fly device configuration. A 10MHz
master clock is required by the DSP engine. The de-
vices’ dual channel architecture supports full duplex,
dual compression or dual expansion operation. The
PCM data interfaces support 1.544, 2.048 and 4.096
MHz data rates. Each device samples the serial PCM or
ADPCM bit stream during a user-programmed input
timeslot, processes the data and outputs the result dur-
ing a user-programmed output timeslot.
Each PCM interface has a control register which speci-
fies functional characteristics (compress, expand, by-
pass and idle), data format (µ-law or A-law) and algo-
rithm reset control. With the SPS pin strapped high, the
software mode is enabled and the serial port is used to
program control and timeslot registers. In this mode, a
novel addressing scheme allows multiple devices to
share a common 3-wire control bus, simplifying system
level interconnect.
With SPS low, the hardware mode is enabled. This
mode disables the serial port and maps appropriate
control register bits to address and port inputs. Under
hardware mode, no host controller is required and all
PCM I/O defaults to timeslot 0. This stand-alone mode is
compatible with popular codecs.
DS2168 BLOCK DIAGRAM
Figure 1
FSX
CLKX
XIN
XOUT
“X” SIDE PCM/ADPCM
DATA INTERFACE
SCLK
SPS
CS
SDI
A0 - A5
SERIAL PORT CONTROL/
HARDWARE MODE LOGIC
ADPCM
PROCESSING
“ENGINE”
MCLK
RST
TM0
TM1
RESET AND TEST LOGIC
V
DD
V
SS
FSY
CLKY
YIN
“Y” SIDE PCM/ADPCM
DATA INTERFACE
YOUT
022698 2/15
DS2167/DS2168
PIN DESCRIPTION
Table 1
PIN
1
SYMBOL
RST
TYPE
I
DESCRIPTION
Reset.
A high-low-high transition clears all internal registers and reset both algo-
rithms. The device should be reset on system power-up, and/or when changing
to/from hardware mode.
Test Modes 0 and 1.
Tie to V
SS
for normal operation
Address Select.
A0=LSB; A5=MSB. Must match address/command word to en-
able serial port write.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TM0
TM1
A0
A1
A2
A3
A4
A5
SPS
MCLK
VSS
XIN
CLKX
FSX
XOUT
SCLK
SDI
CS
YOUT
FSY
CLKY
YIN
VDD
I
I
I
I
–
I
I
I
O
I
I
I
O
I
I
I
–
Serial Port Select.
Tie to V
DD
to select the serial port, to V
SS
to select the hard-
ware mode.
Master Clock.
10 MHz clock for ADPCM processing “engine”; may asynchronous
to SCLK, CLKX and CLKY.
Signal Ground.
0.0 volts
X Data In.
Samples on falling edge of CLKX during selected timeslots.
X Data Clock.
Data clock for X side PCM interface; must be coherent and rising
edge aligned with FSX.
X Frame Sync.
8 KHz frame sync for X side PCM interface.
X Data Out.
Updated on rising edge of CLKX during selected timeslots.
Serial Data Clock.
Used to write serial port registers.
Serial Data In.
Data for onboard control registers. Sampled on rising edge of
SCLK.
Chip Select.
Must be low to write the serial port.
Y Data Out.
Updated on rising edge of CLKY during selected timeslots.
Y Frame Sync.
8 KHz frame sync for Y side PCM interface.
Y Data Clock.
Data clock for Y side PCM interface; must be coherent and rising
edge aligned with FSY.
Y Data In.
Samples on falling edge of CLKY during selected timeslots.
Positive Supply.
5.0 volts.
HARDWARE RESET
RST allows the user to reset both channel algorithms
and register contents. This input must be held low for at
least 1 ms on system power-up after master clock is
stable to assure proper initialization of the device. RST
should also be asserted when changing to/from the
hardware mode. RST clears all bits of the control regis-
ter except IPD; IPD is set for both channels, powering
down the device.
022698 3/15
DS2167/DS2168
HARDWARE MODE
The hardware mode is intended for preliminary system
prototyping or for applications which do not require the
features of the serial port. Tying SPS to VSS disables
the serial port, clears all internal registers and maps
IPD,
µ/A
and CP/EX of the X and Y side interfaces to the
port and address inputs. Input and output timeslots for
the X and Y side interfaces are fixed at 0. Such applica-
tions include, but are not limited to: 1) systems in which
timeslot and algorithm are fixed, 2) stand-alone ADPCM
combo applications, 3) “hardware” oriented systems
where no host controller is available.
HARDWARE MODE
Table 2
PIN #/NAME
4/A0
REG. LOCATION
CP/EX (X)
NAMES AND DESCRIPTION
Channel X coding
0 = Expand
1 = Compress
6/A2
µ/A
(X)
Channel X data format
0 = A-law
1 =
µ-law
7/A3
CP/EX (Y)
Channel Y coding
0 = Expand
1 = Compress
9/A5
µ/A
(Y).2
Channel Y data format
0 = A-law
1 =
µ-law
18/SDI
IPD (Y)
Y idle select
0 = Channel active
1 = Channel idle
19/CS
IPD (X)
X idle select
0 = Channel active
1 = Channel idle
NOTES:
1. SCLK, A1 and A4 must be tied to VSS when the hardware mode is selected.
2. When both X and Y sides are idled, the devices enter a stand-by mode which significantly reduces power
consumption.
3. The DS2167 will power-up within 200 ms after the X or Y side is reactivated (SDI and/or CS not equal to 0)
from standby.
4. The DS2168 must be hardware reset when reactivated from standby. Power-up occurs immediately after the
reset.
022698 4/15
DS2167/DS2168
CODEC/FILTER HARDWARE MODE INTERCONNECT
Figure 2
POWER ON RESET
(DS1231)
TRANSMIT FRAME SYNC
TRANSMIT DATA CLOCK
RST
VCC
-5.0 V
VBB
CODEC/FILTER
GNDA
MCLKX
DX
FSX
BCLKX
DR
FSR
BCLK/
CLKSEL
MCLK/PDN
VFRO
SCLK
XIN
FSX
DS2167/DS2167
CLKX
YOUT
FSY
CLKY
VDD
A0
TP3054 (µ-LAW)
A5
A2
XOUT
YIN
A3
A4
A1
TRANSMIT DATA
RECEIVE DATA
TP3057 (µ-LAW)
TSX
TRANSMIT
ANALOG
INTERFACE
VFXI+
VFSI-
GSX
RECEIVE
ANALOG
INTERFACE
SPS
POWER DOWN
TM0
TM1
VSS
SDI
CS
MCLK
10 MHz CLOCK
ACTIVE
RECEIVE DATA CLOCK
RECEIVE FRAME SYNC
NOTE:
Suggested Codec/Filters
TP305X
National Semiconductor
ETC505X
SGS–Thomson Microelectronics
MC1455XX
Motorola
TCM29CXX Texas Instruments
HD44238C
Hitachi
*other generic Codec/Filter devices can be substituted.
SOFTWARE MODE
Tying SPS high enabled the software mode. In this
mode, a host microcontroller writes configuration data
to the DS2167/DS2168 serial port via inputs SCLK, SDI,
and CS. Independent control and timeslot registers es-
tablish operating characteristics for the X-side and Y-
side PCM interfaces.
A0–A5. If no match occurs, the device ignores the fol-
lowing configuration data. If an address match occurs,
the next three bytes written are accepted as control, in-
put and output timeslot data. Bit ACB.6 determines
which side (X or Y) of the device is to be updated.
CONTROL REGISTER
The control register establishes idle, algorithm reset,
bypass, data format and channel coding for the selected
PCM interface.
The X and Y side PCM interfaces may be independently
disabled (output tri-stated) via IPD; when IPD is set for
ADDRESS/COMMAND BYTE
In the software mode, the address/command byte is the
first byte written to the serial port; it identifies which of 64
possible ADPCM processors sharing the port wiring is
to be updated. Address data must match that at inputs
022698 5/15
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