74ACTQ153 Quiet Series Dual 4-Input Multiplexer
July 1990
Revised March 2001
74ACTQ153
Quiet Series Dual 4-Input Multiplexer
General Description
The ACTQ153 is a high-speed dual 4-input multiplexer with
common select inputs and individual enable inputs for each
section. It can select two lines of data from four sources.
The two buffered outputs present data in the true (non-
inverted) form. In addition to multiplexer operation, the
ACTQ153 can act as a function generator and generate
any two functions of three variables.
Features
s
Outputs source/sink 24 mA
s
ACTQ153 has TTL-compatible inputs
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Improved latch-up immunity
Ordering Code:
Order Number
74ACTQ153SC
74ACTQ153PC
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
I
0a
- 1
3a
I
0b
- 1
3b
S
0
, S
1
E
a
E
b
Z
a
Z
b
Description
Side A Data Inputs
Side B Data Inputs
Common Select Inputs
Side A Enable Input
Side B Enable Input
Side A Output
Side B Output
FACT, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 2001 Fairchild Semiconductor Corporation
DS010244
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74ACTQ153
Functional Description
The ACTQ153 is a dual 4-input multiplexer. It can select
two bits of data from up to four sources under the control of
the common Select inputs (S
0
, S
1
). The two 4-input multi-
plexer circuits have individual active-LOW Enables (E
a
, E
b
)
which can be used to strobe the outputs independently.
When the Enables (E
a
, E
b
) are HIGH, the corresponding
outputs (A
z
, Z
b
) are forced LOW. The ACTQ153 is the logic
implementation of a 2-pole, 4-position switch, where the
position of the switch is determined by the logic levels sup-
plied to the Select inputs. The logic equations for the out-
puts are shown below.
Z
a
=
E
a
• (I
0a
• S
1
• S
0
+
I
1a
• S
1
• S
0
+
I
2a
• S
1
•S
0
+
I
3a
• S
1
• S
0
)
Z
b
=
E
b
• (I
0b
• S
1
• S
0
• I
1b
• S
1
• S
0
+
I
2b
• S
1
• S
0
+
I
3b
• S
1
• S
0
)
Truth Table
Select
Inputs
S
0
X
L
L
H
H
L
L
H
H
S
1
X
L
L
L
L
H
H
H
H
E
H
L
L
L
L
L
L
L
L
Inputs (a or b)
I
0
X
L
H
X
X
X
X
X
X
I
1
X
X
X
L
H
X
X
X
X
I
2
X
X
X
X
X
L
H
X
X
I
3
X
X
X
X
X
X
X
L
H
Outputs
Z
L
L
H
L
H
L
H
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74ACTQ153
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −
0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −
0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latch-Up Source or Sink Current
Junction Temperature (T
J
)
PDIP
140
°
C
−
0.5V to
+
7.0V
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
±
50 mA
±
50 mA
−
65
°
C to
+
150
°
C
±
300 mA
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate
∆
V/
∆
t
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
4.5V to 5.5V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
CCT
I
OLD
I
OHD
I
CC
V
OLP
V
OLV
V
IHD
V
ILD
Maximum Input Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent Supply Current
Maximum HIGH Level
Output Noise
Maximum LOW Level Output Noise
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
5.5
5.5
5.5
5.5
5.5
5.0
5.0
5.0
5.0
1.1
−0.6
1.9
1.2
8.0
1.5
−1.2
2.2
0.8
0.6
0.001
0.001
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±0.1
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±1.0
1.5
75
−75
80.0
µA
µA
mA
mA
µA
V
V
V
V
V
Units
V
V
V
Conditions
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
V
I
OH
= −24
mA
I
OH
= −24
mA (Note 2)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
V
I
OL
=
24 mA
I
OL
=
24 mA (Note 2)
V
I
=
V
CC
, GND
V
I
=
V
CC
−
2.1V
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
Figures 1, 2
(Note 4)(Note 5)
Figures 1, 2
(Note 4)(Note 6)
(Note 4)(Note 6)
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 4:
Worst case package.
Note 5:
Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One Data Input @ V
IN
=
GND.
Note 6:
Max number of Data Inputs (n) switching. (n−1) inputs switching 0V to 5V. Input-under-test switching:
5V to threshold (V
ILD
), 0V to threshold (V
IHD
), f
=
1 MHz.
3
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74ACTQ153
AC Electrical Characteristics
V
CC
Symbol
Parameter
(V)
(Note 7)
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Propagation Delay
S
n
to Z
n
Propagation Delay
S
n
to Z
n
Propagation Delay
E
n
to Z
n
Propagation Delay
E
n
to Z
n
Propagation Delay
I
n
to Z
n
Propagation Delay
I
n
to Z
n
Note 7:
Voltage Range 5.0 is 5.0V
±
0.5V
T
A
= +25°C
C
L
=
50 pF
Min
3.0
3.0
2.0
3.0
2.5
2.0
Typ
7.0
7.0
6.5
6.0
5.5
5.5
Max
11.5
11.5
10.5
9.5
9.5
9.5
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
2.0
2.5
2.0
2.5
2.0
2.0
Max
13.5
13.5
12.5
11.0
11.0
11.0
ns
ns
ns
ns
ns
ns
Units
5.0
5.0
5.0
5.0
5.0
5.0
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
65.0
Units
pF
pF
V
CC
=
5.0V
V
CC
=
5.0V
Conditions
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4
74ACTQ153
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500
Ω
.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
V
OLP
/V
OLV
and V
OHP
/V
OHV
:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50
Ω
coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
• Measure V
OLP
and V
OLV
on the quiet output during the
worst case transition for active and enable. Measure
V
OHP
and V
OHV
on the quiet output during the worst
case active and enable transition.
• Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
V
ILD
and V
IHD
:
• Monitor one of the switching outputs using a 50
Ω
coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
• First increase the input LOW voltage level, V
IL
, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input LOW voltage level at which
oscillation occurs is defined as V
ILD
.
• Next decrease the input HIGH voltage level, V
IH
, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input HIGH voltage level at which
oscillation occurs is defined as V
IHD
.
• Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
Note 8:
V
OHV
and V
OLP
are measured with respect to ground reference.
Note 9:
Input pulses have the following characteristics: f
=
1 MHz, t
r
=
3 ns,
t
f
=
3 ns, skew
<
150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
FIGURE 2. Simultaneous Switching Test Circuit
5
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