74LVQ157 Low Voltage Quad 2-Input Multiplexer
February 1992
Revised June 2001
74LVQ157
Low Voltage Quad 2-Input Multiplexer
General Description
The LVQ157 is a high-speed quad 2-input multiplexer. Four
bits of data from two sources can be selected using the
common Select and Enable inputs. The four outputs
present the selected data in the true (non inverted) form.
The LVQ157 can also be used as a function generator.
Features
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Guaranteed incident wave switching into 75
Ω
.
Ordering Code:
Order Number
74LVQ157SC
74LVQ157SJ
Package Number
M16A
M16D
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
I
0a
–I
0d
I
1a
–I
1d
E
S
Z
a
–Z
d
Description
Source 0 Data Inputs
Source 1 Data Inputs
Enable Input
Select Input
Outputs
© 2001 Fairchild Semiconductor Corporation
DS011352
www.fairchildsemi.com
74LVQ157
Truth Table
Inputs
E
H
L
L
L
L
S
X
H
H
L
L
I
0
X
X
X
L
H
I
1
X
L
H
X
X
Outputs
Z
L
L
H
L
H
Functional Description
The LVQ157 is a quad 2-input multiplexer. It selects four
bits of data from two sources under the control of a com-
mon Select input (S). The Enable input (E) is active-LOW.
When E is HIGH, all of the outputs (Z) are forced LOW
regardless of all other inputs. The LVQ157 is the logic
implementation of a 4-pole, 2-position switch where the
position of the switch is determined by the logic levels sup-
plied to the Select input. The logic equations for the outputs
are shown below:
Z
a
=
E • (I
1a
• S
+
I
0a
• S)
Z
b
=
E • (I
1b
• S
+
I
0b
• S)
Z
c
=
E • (I
1c
• S
+
I
0c
• S)
Z
d
=
E • (I
1d
• S
+
I
0d
• S)
A common use of the LVQ157 is the moving of data from
two groups of registers to four common output busses. The
particular register from which the data comes is determined
by the state of the Select input. A less obvious use is as a
function generator. The LVQ157 can generate any four of
the sixteen different functions of two variables with one
variable common. This is useful for implementing gating
functions.
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
74LVQ157
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −
0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −
0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
(I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latch-Up Source or
Sink Current
−
0.5V to
+
7.0V
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
±
50 mA
±
200 mA
−
65
°
C to
+
150
°
C
±
100 mA
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
V/
∆
t)
V
IN
from 0.8V to 2.0V
V
CC
@ 3.0V
125 mV/ns
2.0V to 3.6V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
V
OL
Maximum Low Level
Output Voltage
I
IN
I
OLD
I
OHD
I
CC
V
OLP
V
OLV
V
IHD
V
ILD
Maximum Input
Leakage Current
Minimum Dynamic
Output Current (Note 4)
Maximum Quiescent
Supply Current
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Maximum High Level
Dynamic Input Voltage
Maximum Low Level
Dynamic Input Voltage
V
CC
(V)
3.0
3.0
3.0
3.0
3.0
3.0
3.6
3.6
3.6
3.6
3.3
3.3
3.3
3.3
0.7
−0.4
1.7
1.6
4.0
0.8
−0.8
2.0
0.8
0.002
T
A
= +25°C
Typ
1.5
1.5
2.99
2.0
0.8
2.9
2.58
0.1
0.36
±0.1
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
0.8
2.9
2.48
0.1
0.44
±1.0
36
−25
40.0
V
V
V
V
V
V
µA
mA
mA
µA
V
V
V
V
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
(Note 3)
I
OH
= −12
mA
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
(Note 3)
I
OL
=
12 mA
V
I
=
V
CC
,
GND
V
OLD
=
0.8V Max (Note 5)
V
OHD
=
2.0V Min (Note 5)
V
IN
=
V
CC
or GND
(Note 6)(Note 7)
(Note 6)(Note 7)
(Note 6)(Note 8)
(Note 6)(Note 8)
Units
Conditions
Note 3:
All outputs loaded; thresholds on input associated with output under test.
Note 4:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 5:
Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for.
Note 6:
Worst case package.
Note 7:
Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8:
Max number of Data Inputs (n) switching. (n
−
1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f
=
1 MHz.
3
www.fairchildsemi.com
74LVQ157
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
V
CC
(V)
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
OSHL,
t
OSLH
Propagation Delay
S to Z
n
Propagation Delay
S to Z
n
Propagation Delay
E to Z
n
Propagation Delay
E to Z
n
Propagation Delay
I
n
to Z
n
Propagation Delay
I
n
to Z
n
Output to Output Skew (Note 9)
Data to Output
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
C
L
=
50 pF
Typ
84
7.0
7.8
6.5
8.4
7.0
7.8
6.5
6.0
5.0
6.0
5.0
1.0
1.0
Max
16.2
11.5
15.5
11.0
16.2
11.5
15.5
11.0
12.0
8.5
11.3
8.0
1.5
1.5
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.0
1.0
1.0
1.0
Max
19.0
13.0
17.0
12.0
19.0
13.0
17.0
12.0
13.0
9.0
13.0
9.0
1.5
1.5
ns
ns
ns
ns
ns
ns
ns
Units
Note 9:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
Capacitance
Symbol
C
IN
C
PD
(Note 10)
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
34.0
Units
pF
pF
V
C
=
Open
V
CC
=
3.3V
Conditions
Note 10:
C
PD
is measured at 10 MHz.
www.fairchildsemi.com
4
74LVQ157
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
5
www.fairchildsemi.com
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
