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TN80960SB16: 产品描述IC mpu i960sb 16mhz 84-plcc; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小2MB，共38页; 制造商Intel(英特尔); 官网地址http://www.intel.com/

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TN80960SB16概述

IC mpu i960sb 16mhz 84-plcc

TN80960SB16规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	Intel(英特尔)
包装说明	QCCJ, LDCC84,1.2SQ
Reach Compliance Code	unknown
位大小	32
JESD-30 代码	S-PQCC-J84
JESD-609代码	e0
端子数量	84
封装主体材料	PLASTIC/EPOXY
封装代码	QCCJ
封装等效代码	LDCC84,1.2SQ
封装形状	SQUARE
封装形式	CHIP CARRIER
电源	5 V
认证状态	Not Qualified
速度	16 MHz
最大压摆率	350 mA
标称供电电压	5 V
表面贴装	YES
技术	CMOS
端子面层	Tin/Lead (Sn/Pb)
端子形式	J BEND
端子节距	1.27 mm
端子位置	QUAD
uPs/uCs/外围集成电路类型	MICROPROCESSOR, RISC
Base Number Matches	1

文档解析

80960SB处理器是Intel公司i960® 32位处理器家族的一员，专为低成本嵌入式应用设计。它包含了一个集成的浮点单元（FPU），这使得它在处理需要浮点运算的应用时具有优势。以下是一些利用80960SB处理器的浮点性能来优化算法的方法：

充分利用浮点单元：80960SB的浮点单元完全符合IEEE 754标准，支持单精度（32位）、双精度（64位）和扩展精度（80位）浮点数的运算。确保算法中所有浮点运算都通过这个单元来执行，以提高性能。
代码优化：使用针对80960SB优化的编译器，它能够生成更有效的代码。编译器通常能够优化浮点运算的顺序和存储，减少不必要的内存访问。
算法选择：选择适合浮点运算的算法。例如，在数字信号处理、图像处理或科学计算中，选择那些能够充分利用浮点性能的算法。
并行处理：80960SB拥有多个并行执行单元，可以同时执行多个操作。在设计算法时，考虑如何将算法分解为可以并行处理的部分。
缓存利用：80960SB有一个512字节的指令缓存，并且支持数据缓存。确保频繁访问的数据和指令被缓存，以减少访问时间。
寄存器使用：80960SB有多个寄存器集，包括全局和本地寄存器。合理使用这些寄存器可以减少对内存的访问，提高数据处理速度。
中断和异常处理：合理配置和优化中断处理程序，确保它们不会过多地干扰浮点运算的执行。
测试和调试：使用80960SB的内置调试功能，如硬件断点和跟踪模式，来测试和调试浮点运算密集的代码，确保算法的正确性和性能。
内存管理：合理管理内存，确保浮点数据的存储和访问是高效的。使用合适的数据结构和内存访问模式来减少延迟。
系统时钟配置：根据应用需求合理配置系统时钟频率，以达到性能和功耗的平衡。

通过上述方法，可以充分利用80960SB处理器的浮点性能，从而优化嵌入式系统中的算法。

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80960SB

EMBEDDED 32-BIT MICROPROCESSOR

WITH 16-BIT BURST DATA BUS

■

High-Performance Embedded Architecture

■

Built-in Interrupt Controller

— 16 MIPS* Burst Execution at 16 MHz

— 5 MIPS Sustained Execution at 16 MHz

■

512-Byte On-Chip Instruction Cache

— Direct Mapped

— Parallel Load/Decode for Uncached

Instructions

■

Multiple Register Sets

— Sixteen Global 32-Bit Registers

— Sixteen Local 32-Bit Registers

— Four Local Register Sets Stored

On-Chip

— Register Scoreboarding

■

Pin Compatible with 80960SA

— 4 Direct Interrupt Pins

— 31 Priority Levels, 256 Vectors

■

Built-In Floating Point Unit

— Fully IEEE 754 Compatible

■

Easy to Use, High Bandwidth 16-Bit Bus

— 25.6 Mbytes/s Burst

— Up to 16 Bytes Transferred per Burst

■

32-Bit Address Space, 4 Gigabytes

■

80-Lead Quad Flat Pack (EIAJ QFP)

— 84-Lead Plastic Leaded Chip Carrier

(PLCC)

■

Software Compatible with

80960KA/KB/CA/CF Processors

The 80960SB is a member of Intel’s i960

32-bit processor family, which is designed especially for low cost

embedded applications. It includes a 512-byte instruction cache, an integrated floating-point unit and a built-in

interrupt controller. The 80960SB has a large register set, multiple parallel execution units and a 16-bit burst

bus. Using advanced RISC technology, this high performance processor is capable of execution rates in excess

of 5 million instructions per second

. The 80960SB is well-suited for a wide range of cost sensitive embedded

applications including non-impact printers, network adapters and I/O controllers.

FOUR

80-BIT FP

REGISTERS

80-BIT

FPU

SIXTEEN

32-BIT GLOBAL

REGISTERS

64- BY 32-BIT

LOCAL

CACHE

32-BIT

INSTRUCTION

EXECUTION

UNIT

INSTRUCTION

FETCH UNIT

512-BYTE

INSTRUCTION

CACHE

INSTRUCTION

DECODER

MICRO-

INSTRUCTION

SEQUENCER

MICRO-

INSTRUCTION

ROM

32-BIT

BUS

CONTROL

LOGIC

32-BIT

ADDRESS

16-BIT

BURST

BUS

Figure 1. The 80960SB Processor’s Highly Parallel Architecture

* Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment

Corporation)

Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent

licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.

August 2004

Order Number: 272207-003

80960SB

EMBEDDED 32-BIT MICROPROCESSOR

WITH 16-BIT BURST DATA BUS

CONTENTS

PAGE

1.0 THE i960

PROCESSOR

...........................................................................................................................1

1.1 Key Performance Features .................................................................................................................2

1.1.1 Memory Space And Addressing Modes ................................................................................... 4

1.1.2 Data Types ...............................................................................................................................4

1.1.3 Large Register Set ...................................................................................................................4

1.1.4 Multiple Register Sets ..............................................................................................................5

1.1.5 Instruction Cache .....................................................................................................................5

1.1.6 Register Scoreboarding ........................................................................................................... 5

1.1.7 Floating-Point Arithmetic .......................................................................................................... 6

1.1.8 High Bandwidth Bus ................................................................................................................6

1.1.9 Interrupt Handling ....................................................................................................................7

1.1.10 Debug Features .....................................................................................................................7

1.1.11 Fault Detection .......................................................................................................................7

1.1.12 Built-in Testability ...................................................................................................................7

1.1.13 CHMOS .................................................................................................................................. 7

2.0 ELECTRICAL SPECIFICATIONS.............................................................................................................

2.1 Power and Grounding ....................................................................................................................... 11

2.2 Power Decoupling Recommendations .............................................................................................. 11

2.3 Connection Recommendations ......................................................................................................... 11

2.4 Characteristic Curves ....................................................................................................................... 11

2.5 Test Load Circuit ............................................................................................................................... 13

2.6 ABSOLUTE MAXIMUM RATINGS* .................................................................................................. 14

2.7 DC Characteristics ............................................................................................................................ 14

2.8 AC Specifications .............................................................................................................................. 15

3.0 MECHANICAL DATA

............................................................................................................................... 20

3.1 Packaging ......................................................................................................................................... 20

3.2 Pin Assignment ................................................................................................................................. 20

3.3 Pinout ................................................................................................................................................ 22

3.4 Package Thermal Specifications ...................................................................................................... 26

4.0 WAVEFORMS

........................................................................................................................................... 27

5.0 REVISION HISTORY

................................................................................................................................ 33

LIST OF FIGURES

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

PAGE

The 80960SB Processor’s Highly Parallel Architecture ................................................................ 0

80960SB Programming Environment ........................................................................................... 1

Instruction Formats ...................................................................................................................... 4

Multiple Register Sets Are Stored On-Chip .................................................................................. 6

Connection Recommendation for LOCK .................................................................................... 11

Typical Supply Current vs. Case Temperature ........................................................................... 12

Typical Current vs. Frequency (Room Temp) ............................................................................. 12

Typical Current vs. Frequency (Hot Temp) ................................................................................. 13

Capacitive Derating Curve ......................................................................................................... 13

Test Load Circuit for Three-State Output Pins ............................................................................ 13

Drive Levels and Timing Relationships for 80960SB Signals ..................................................... 15

Processor Clock Pulse (CLK2) ................................................................................................... 18

RESET Signal Timing ................................................................................................................. 18

HOLD Timing .............................................................................................................................. 19

80-Lead EIAJ Quad Flat Pack (QFP) Package .......................................................................... 20

84-Lead Plastic Leaded Chip Carrier (PLCC) Package ............................................................. 21

Non-Burst Read and Write Transactions Without Wait States .................................................... 27

Quad Word Burst Read Transaction With 1, 0, 0, 0, 0, 0, 0, 0 Wait States ................................ 28

Burst Write Transaction With 2, 1, 1, 1 Wait States (6-8 Bytes Transferred) .............................. 29

Accesses Generated by Quad Word Read Bus Request,

Misaligned One Byte from Quad Word Boundary 1, 0, 0, 0, 0, 0, 0, 0 Wait States

Interrupt Acknowledge Cycle ...................................................................................................... 31

Cold Reset Waveform ................................................................................................................ 32

LIST OF TABLES

Table 1

Table 2

Table 3

Table 4

Table 5

Table 6

Table 7

Table 8

Table 9

Table 10

Table 11

Table 12

Table 13

Table 14

80960SB Instruction Set .............................................................................................................. 3

Memory Addressing Modes ......................................................................................................... 4

Sample Floating-Point Execution Times (µs) at 16 MHz .............................................................. 6

80960SB Pin Description: Bus Signals ........................................................................................ 8

80960SB Pin Description: Support Signals ................................................................................ 10

DC Characteristics ..................................................................................................................... 14

80960SB AC Characteristics (10 MHz) ...................................................................................... 16

80960SB AC Characteristics (16 MHz) ...................................................................................... 17

80960SB QFP Pinout — In Pin Order ........................................................................................ 22

80960SB QFP Pinout — In Signal Order ................................................................................... 23

80960SB PLCC Pinout — In Pin Order ...................................................................................... 24

80960SB PLCC Pinout — In Signal Order ................................................................................. 25

80960SB QFP Package Thermal Characteristics ...................................................................... 26

80960SB PLCC Package Thermal Characteristics .................................................................... 26

iii

TN80960SB16相似产品对比

	TN80960SB16	N80960SB16	EE80960SB10512	N80960SB10	EN80960SB16512
描述	IC mpu i960sb 16mhz 84-plcc	IC mpu i960sb 16mhz 84-plcc	IC mpu i960sb 10mhz 84-plcc	IC mpu i960sb 10mhz 84-plcc	IC mpu i960sb 16mhz 84-plcc
是否Rohs认证	不符合	不符合	-	不符合	-
厂商名称	Intel(英特尔)	Intel(英特尔)	-	Intel(英特尔)	-
包装说明	QCCJ, LDCC84,1.2SQ	QCCJ, LDCC84,1.2SQ	-	QCCJ, LDCC84,1.2SQ	-
Reach Compliance Code	unknown	compliant	-	compliant	-
位大小	32	32	-	32	-
JESD-30 代码	S-PQCC-J84	S-PQCC-J84	-	S-PQCC-J84	-
JESD-609代码	e0	e0	-	e0	-
端子数量	84	84	-	84	-
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	-
封装代码	QCCJ	QCCJ	-	QCCJ	-
封装等效代码	LDCC84,1.2SQ	LDCC84,1.2SQ	-	LDCC84,1.2SQ	-
封装形状	SQUARE	SQUARE	-	SQUARE	-
封装形式	CHIP CARRIER	CHIP CARRIER	-	CHIP CARRIER	-
电源	5 V	5 V	-	5 V	-
认证状态	Not Qualified	Not Qualified	-	Not Qualified	-
速度	16 MHz	16 MHz	-	10 MHz	-
最大压摆率	350 mA	350 mA	-	280 mA	-
标称供电电压	5 V	5 V	-	5 V	-
表面贴装	YES	YES	-	YES	-
技术	CMOS	CMOS	-	CMOS	-
端子面层	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	-
端子形式	J BEND	J BEND	-	J BEND	-
端子节距	1.27 mm	1.27 mm	-	1.27 mm	-
端子位置	QUAD	QUAD	-	QUAD	-
uPs/uCs/外围集成电路类型	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	-	MICROPROCESSOR, RISC	-
Base Number Matches	1	1	-	1	-

TN80960SB16

TN80960SB16概述

TN80960SB16规格参数

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