CTSLV310
Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator
SON8, MSOP8
FEATURES
2.5V-3.3V Operation
Ultra-Low Phase Noise Floor
o
LVPECL -167dBc/Hz
o
LVDS -165dBc/Hz
Configurable
o
LVPECL or LVDS Output
o
÷1 or ÷2
o
Enable Active High or Low
1GHz+ Bandwidth
RoHS Compliant Pb Free Packages
BLOCK DIAGRAM
DESCRIPTION
The CTSLV310 is a configurable LVPECL, LVDS buffer & translator IC that is optimized for ultra-low
phase noise and 2.5V-3.3V nominal supply voltage. It is particularly useful in converting crystal or
SAW based oscillators into LVPECL and LVDS outputs for up to 1GHz of bandwidth. For a design that
includes gain in the signal path, refer to the
CTSLV315.
A configurable IC design capable of providing LVPECL or LVDS outputs, ÷1 or ÷2 function, and active
high or active low enable selection. See Table 1 for details of the configurations options that provide
designers with a single IC buffer/translator solution that is extremely compact, flexible and high
performance.
8 configurations which are determined by the static voltage levels of b-0 and b-1. Table 1 details the
configurations.
Table 1 - Possible IC Configuration
Configuration Bits
b-0
Open
Open
Open
Low
Low
Low
High
High
High
b-1
Open
Low
High
Open
Low
High
Open
Low
High
Functional Configuration
Output Type
LVPECL
LVPECL
LVPECL
LVPECL
LVDS
LVDS
LVDS
LVDS
Not Used
Enable Polarity
Active High
Active High
Active Low
Active Low
Active High
Active High
Active Low
Active Low
Not Used
Division
÷1
÷2
÷1
÷2
÷1
÷2
÷1
÷2
Not Used
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
1
RevA0215
CTSLV310
Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator
SON8, MSOP8
Input Termination
The D input bias is V
DD
/2 fed through an internal 10k resistor. For clock applications, an input signal of at
least 750m V
PP
ensures the CTSLV10 meets AC specifications. The input should also be AC coupled to
maintain a 50% duty cycle on the outputs. The input can be driven to any voltage between 0V and V
DD
without
damage or waveform degradation.
LVPECL Output Termination Techniques
DC Coupling
The LVPECL compatible output stage of the CTSLV310 uses a current drive topology to maximize switching
speed as illustrated below. Two current source PMOS transistors (M1-M2) feed the output pins. M5 is an
NMOS current source which is switched by M3 and M4. When M4 is on, M5 takes current from M2. This
produces an output current of 5.1mA (low output state). M3 is off, and the entire 21.1mA flows through the
output pin. The associated output voltage swings match LVPECL levels when external 50 resistors
terminate the outputs.
Both Q and QN should always be terminated identically to avoid waveform distortion and circulating current
caused by unsymmetrical loads. This rule should be followed even if only one output is in use.
V
DD
Output
Stage
V
bp
M1
M2
External
Circuitry
21.1mA
Q
QN
21.1mA
D
M3
M4
21.1mA - High
5.1mA - Low
50Ω
50Ω
V
bn
M5
16mA
V
TT
= V
DD
- 2.0V
Typical Output Termination
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
2
RevA0215
CTSLV310
Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator
SON8, MSOP8
AC Coupling
Clock applications or phase noise/frequency domain testing scenarios typically require AC coupling. The
illustration below shows the AC coupling technique. The 200 resistors form the required DC loads, and the
50 resistors provide the AC termination. The parallel combination of the 200 and 50 resistors results in a
net 40 AC load termination. In many cases this will work well. If necessary, the 50 resistors can be
increased to about 56. Alternately, bias tees combined with current setting resistors will eliminate the
lowered AC load impedance. The 50 resistors are typically connected to ground but can be connected to the
bias level needed by the succeeding stage.
V
DD
Output
Stage
V
bp
M1
M2
External
Circuitry
21.1mA
Q
QN
0.01µF
0.01µF
21.1mA
D
M3
M4
21.1mA - High
5.1mA - Low
200Ω
200Ω
50Ω
50Ω
V
bn
M5
16mA
GND or V
T
AC Termination
LVDS Output Termination Technique
The following LVDS termination is compliant to the LVDS specification
TIA/EIA-644A.
LVDS Termination
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
3
RevA0215
CTSLV310
Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator
SON8, MSOP8
ELECTRICAL SPECIFICATIONS
Absolute Maximum Rating
Symbol
V
DD
V
ABSOLUTE
T
OP
T
STORAGE
Characteristic
Supply Voltage
Absolute Max Power Supply
Operating Temperature
Range
Storage Temperature Range
D
EN
b0
b1
b-0, b-1 = V
DD
b-0, b-1 = GND
Continuous
t
≤
1s
-40
-65
-0.5
-0.5
-0.5
-0.5
-11
V
DD
-0.5
0
-4
V
DD
-0.5
0
Human Body Model
Machine Model
Charged Device
Model
2000
200
2000
V
DD
0.5
3
V
DD
0.5
uA
V
Conditions
Min
2.375
Typ
2.5
3.3
Max
3.6
3.6
5.5
85
150
V
DD
+0.5
V
DD
+ 0.5
V
DD
+ 0.5
V
DD
+ 0.5
11
Unit
V
V
°C
°C
V
I_MAX
Maximum Input Voltages
V
I
b0,b1
Vt
b0,b1
I
EN
Vt
EN
b-0, b-1 Input High Current
b-0, b-1 Input Low Current
b-0, b-1 Input High Voltage
Threshold
b-0, b-1 Input Low Voltage
Threshold
EN Input Current
EN Input High Voltage
Threshold
EN Input Low Voltage
Threshold
ESD Ratings
uA
V
ESD
V
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
4
RevA0215
CTSLV310
Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator
SON8, MSOP8
LVPECL Performance Specifications
Symbol
f
MAX
R
L
R
BIAS
V
IN_SWING
Characteristic
Max Input Frequency
Output Loading
Input Bias Resistor
Input Voltage Swing
Conditions
÷1 mode
÷2 mode
D input to V
DD
/2 ref
minimum
1
recommended
1
V
DD
= 2.5V, HIGH
V
DD
= 2.5V, LOW
V
DD
= 3.3V, HIGH
V
DD
= 3.3V, LOW
V
DD
= 2.5V
V
OD
Differential Output Voltage
V
DD
= 3.3V
t
R
/ t
F
PN
J
INTEG
T
ENABLE
T
DISABLE
T
PROP
I
DD
1
2
3
4
5
Min
1000
1600
Typ
Max
Unit
MHz
50
10k
0.2
0.6
V
DD
-1.25
V
DD
-1.86
V
DD
-1.15
V
DD
-1.86
0.54
0.75
0.74
3.49
100
-167
26
15
0.5
2.2
28.5
5
Ω
Ω
V
PP
V
DD
-0.88
V
DD
-1.66
V
DD
-0.88
V
DD
-1.75
0.93
5.47
0.93
5.47
205
V
V
V
V
V
PP
, Q/QN
dBm,
Q/QN
V
PP
, Q/QN
dBm,
Q/QN
ps
dBc/Hz
ƒs
us
us
ns
mA
V
OUT
Voltage Output Levels
Output Rise/Fall Time
Phase Noise Floor
Integrated Jitter:
12kHz-20MHz
Enable Time
2
Disable Time
2
Propagation Delay
3
Power Supply Current
80%-20%
1MHz Offset
155MHz Carrier
EN = active
EN = disabled
0.9
EN = active
4
EN = disabled
5
Phase noise floor performance is dependent upon input voltage swing. Voltage swing values
below recommended values may result in degraded phase noise values.
Into and out of tri-state condition.
Time from D crossing V
DD
/2 to Q=QN.
V
DD
=3.3V, F
IN
@ 200MHz.
D = 0V.
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
5
RevA0215
嵌入式系统
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