IDTCV141
1-TO-8 DIFFERENTIAL CLOCK BUFFER
COMMERCIAL TEMPERATURE RANGE
1-TO-8 DIFFERENTIAL
CLOCK BUFFER
IDTCV141
FEATURES:
•
•
•
•
•
•
•
•
Compliant with Intel DB800 spec
Eight differential clock pairs at 0.7V
50ps skew
50ps cycle-to-cycle jitter
Programmable Bandwidth
PLL bypass configurable
Divide by 2 programmable
Available in SSOP and TSSOP packages
DESCRIPTION:
The CV141 differential buffer is compliant with Intel DB800 specifications. It
is intended to distribute the SRC (serial reference clock) as a companion chip
to the main clock of the CK409, CK410/CK410M, CK410B, etc. PLL is off in
bypass mode and has no clock detect.
FUNCTIONAL BLOCK DIAGRAM
OE_INV
(1)
DIF_0
Output
Control
DIF_0#
DIF_1
DIF_1#
DIF_2
DIF_2#
OE[7:0]
(1)
SRC_STOP
(1)
P
WRDWN
SCL
SDA
SM Bus
Controller
Output
Buffer
DIF_3
DIF_3#
DIF_4
SRC_DIV2#
PLL/BYPASS#
SRC_IN
DIF_4#
DIF_5
DIF_5#
DIF_6
SRC_IN#
DIV
HIGH_BW#
PLL
DIF_6#
DIF_7
DIF_7#
LOCK
NOTE:
1. See OE_INV table for active HIGH or active LOW.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2005 Integrated Device Technology, Inc.
OCTOBER 2005
DSC 6738/19
IDTCV141
1-TO-8 DIFFERENTIAL CLOCK BUFFER
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
SRC_DIV2#
V
DD
V
SS
SRC_IN
SRC_IN#
(1)
(1)
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DDA
Description
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage GND - 0.5
Storage Temperature
Ambient Operating Temperature
Case Temperature
Input ESD Protection
Human Body Model
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Min
Max
4.6
4.6
+150
+70
+115
Unit
V
V
°C
°C
°C
V
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
V
DDA
V
SSA
IREF
LOCK
V
DDIN
T
STG
T
AMBIENT
T
CASE
ESD Prot
(1)
(1)
–65
0
2000
OE_7
OE_4
DIF_7
OE_0
OE_3
DIF_0
DIF_0#
V
SS
V
DD
DIF_1
DIF_1#
(1)
OE_1
(1)
DIF_7#
OE_INV
V
DD
DIF_6
DIF_6#
OE_6
OE_5
DIF_5
DIF_5#
V
SS
V
DD
DIF_4
DIF_4#
HIGH_BW#
SRC_STOP
(1)
P
WRDWN (1)
(1)
(1)
OE_2
OE_INV
OE_[7:0]
P
WRDWN
SRC_STOP
OE_INV = 0
Active HIGH
Active LOW
Active LOW
OE_INV = 1
Active LOW
Active HIGH
Active HIGH
DIF_2
DIF_2#
V
SS
V
DD
DIF_3
DIF_3#
PLL/BPASS#
SCL
HIGH_BW# SELECTION
PLL BW
PLL Peaking
HIGH_BW# = 0
Min. Typ. Max.
2
3
4
—
1
3
HIGH_BW#=1
Min. Typ.
Max.
0.7
1
1.4
—
1
3
Unit
MHz
dB
SDA
V
SS
NOTE:
1. See OE_INV table for active HIGH or active LOW.
SSOP/ TSSOP
TOP VIEW
OE FUNCTIONALITY [OE_INV = 0]
OE_[7:0] - Pin OE_[7:0] - SMBus bit
1
1
1
0
0
1
0
0
DIF_[7:0]
Normal
Tristate
Tristate
Tristate
DIFF_[7:0]#
Normal
Tristate
Tristate
Tristate
OE FUNCTIONALITY [OE_INV = 1]
OE_[7:0] - Pin OE_[7:0] - SMBus bit
1
1
1
0
0
1
0
0
DIF_[7:0]
Tristate
Tristate
Normal
Tristate
DIFF_[7:0]#
Tristate
Tristate
Normal
Tristate
2
IDTCV141
1-TO-8 DIFFERENTIAL CLOCK BUFFER
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name
SRC_IN, SRC_IN#
DIF_[7:0], DIF_ [7:0]#
OE[7:0]
P
WRDWN
IREF
LOCK
PLL/Bypass#
HIGH_BW#
SRC_DIV2#
SRC_STOP
SCL
SDA
OE_INV
Type
IN, DIF
OUT, DIF
IN
IN
IN
OUT
IN
IN
IN
IN
IN
I/O, Open Collector
IN
Pin #
4,5
8, 9, 12, 13, 16, 17,
20, 21, 29, 30, 33,
34, 37, 38, 41, 42
6, 7, 14, 15,
35, 36, 43, 44
26
46
45
22
28
1
27
23
24
40
0.7V differential SRC input
0.7V differential clock output
3.3V LVTTL input for enabling differential outputs (see OE_INV table)
3.3V LVTTL for power down (see OE_INV table)
Reference current for differential output
HIGH, locked
1 = PLL mode, 0 = bypass, PLL OFF
0 = HIGH BW, 1 = LOW BW (see HIGH_BW# Selection table)
LOW = divide by 2 mode
SRC stop (see OE_INV table)
SMBus clock
SMBus data
(see OE_INV table)
Description
INDEX BLOCK WRITE PROTOCOL
Bit
1
2-9
10
11-18
19
20-27
28
29-36
37
38-45
46
# of bits
1
8
1
8
1
8
1
8
1
8
1
From
Master
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Description
Start
DCh
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Nth data byte
Acknowledge
Stop
INDEX BLOCK READ PROTOCOL
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit30-37).
Bit
1
2-9
10
11-18
19
20
21-28
29
30-37
38
39-46
47
48-55
# of bits
1
8
1
8
1
1
8
1
8
1
8
1
8
From
Master
Master
Slave
Master
Slave
Master
Master
Slave
Slave
Master
Slave
Master
Slave
Description
Start
DCh
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Repeated Start
DDh
Ack (Acknowledge)
Byte count, N (block read back of N
bytes), power on is 8
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Ack (Acknowledge)
Nth data byte
Not acknowledge
Stop
Master
Slave
Master
INDEX BYTE WRITE
Setting bit[11:18] = starting address, bit[20:27] = 01h.
INDEX BYTE READ
Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.
3
IDTCV141
1-TO-8 DIFFERENTIAL CLOCK BUFFER
COMMERCIAL TEMPERATURE RANGE
CONTROL REGISTERS
BYTE 0
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
PowerDown dirve mode
SRC_STOP# drive mode
Reserved
Reserved
Reserved
High_BW#
PLL/Bypass#
SRC_DIV2#
Description/Function
0
Driven
Driven
1
Tri-state
Tri-state
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
0
0
0
0
0
1
1
1
Logically AND with HW pin
Logically AND with HW pin
Logically AND with HW pin
High band width
Bypass
Divided by 2
Low band width
PLL mode
Normal
BYTE 1
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
DIFF_7
DIFF_6
DIFF_5
DIFF_4
DIFF_3
DIFF_2
DIFF_1
DIFF_0
Description/Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
0
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
1
1
1
1
1
1
1
1
BYTE 2
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
DIFF_7
DIFF_6
DIFF_5
DIFF_4
DIFF_3
DIFF_2
DIFF_1
DIFF_0
Description/Function
Free Running with SRC_STOP#
Free Running with SRC_STOP#
Free Running with SRC_STOP#
Free Running with SRC_STOP#
Free Running with SRC_STOP#
Free Running with SRC_STOP#
Free Running with SRC_STOP#
Free Running with SRC_STOP#
0
Free
Free
Free
Free
Free
Free
Free
Free
1
stopped
stopped
stopped
stopped
stopped
stopped
stopped
stopped
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
0
0
0
0
0
0
0
0
BYTE 3
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description / Function
0
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
4
IDTCV141
1-TO-8 DIFFERENTIAL CLOCK BUFFER
COMMERCIAL TEMPERATURE RANGE
BYTE 4
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
Description / Function
Revision ID
Revision ID
Revision ID
Revision ID
Vendor ID
Vendor ID
Vendor ID
Vendor ID
0
1
Type
R
R
R
R
R
R
R
R
Power On
0
0
0
0
0
1
0
1
BYTE 62 = 10h
BYTE 63 = 14h
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= 0°C to +70°C, Supply Voltage: V
DD
= 3.3V ± 5%
Symbol
V
IH
V
IL
I
IH
I
IL1
I
IL2
L
PIN
C
IN
C
OUT
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Input LOW Current
Pin Inductance
(2)
Input Capacitance
(2)
Logic inputs
Output pin capacitance
3.3V ± 5%
3.3V ± 5%
V
IN
= V
DD
V
IN
= 0V, inputs with no pull-up resistors
V
IN
= 0V, inputs with pull-up resistors
Test Conditions
Min.
2
V
SS
- 0.3
–5
–5
–200
—
—
—
Typ.
—
—
—
—
—
—
—
—
Max.
V
DD
+ 0.3
0.8
5
—
—
7
5
6
Unit
V
V
µA
µA
µA
nH
pF
5
FPGA/CPLD
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