IDTCV115F
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC™
CLOCK FOR P4 PROCESSOR
IDTCV115F
FEATURES:
One high precision N and SSC programmable PLL for SRC/PCI
One high precision N and SSC programmable PLL for CPU
One high precision SSC programmable PLL for SATA
One high precision PLL for 96MHz/48MHz
Band-gap circuit for differential outputs
Support multiple spread spectrum modulation, down and
center
• Support SMBus block read/write, index read/write
• Selectable output strength for REF, PCI, and USB48MHz
• Available in SSOP package
•
•
•
•
•
•
DESCRIPTION:
IDTCV115F is a 56 pin clock device, complying the latest Intel CK410E
requirements, for Intel advance P4 processors. The CPU output buffer is
designed to support up to 400MHz processor. One dedicated PLL for Serial
ATA clock provides high accuracy frequency. This device also implements
Band-gap referenced I
REF
to reduce the impact of V
DD
variation on differential
outputs, which can provide more robust system performance.
Each CPU/SRC/PCI, SATA clock has its own Spread Spectrum selection,
which allows for isolated changes instead of affecting other clock groups.
KEY SPECIFICATIONS:
• CPU/SRC CLK cycle to cycle jitter < 85ps
• SATA CLK cycle to cycle jitter < 85ps
FUNCTIONAL BLOCK DIAGRAM
SATA PLL
SCC
Programmable
SATA/
SRC4 - SATA
PCI[4:0], PCIF[2:0]
PCI/
14.318MHz
Osc
PCIEX PLL
SCC
N Programmable
PCIE/
SRC[6:5] [3:1]
MUX
CPU PLL
SCC
N Programmable
CPU2_ITP/
SRC7
Host/
CPU[1:0]
48MHz/
USB48
Fixed PLL
No SCC
96MHz/
DOT96
REF
OUTPUT TABLE
CPU
2
CPU2_ITP/SRC
1
SRC
5
SATA
1
PCI/PCIF
8
REF
1
DOT96
1
48MHz
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2005 Integrated Device Technology, Inc.
APRIL 2005
DSC - 6758/8
IDTCV115F
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
V
DD
_PCI
V
SS
_PCI
PCI2
PCI3
PCI4
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage GND - 0.5
Storage Temperature
Ambient Operating Temperature
Case Temperature
Input ESD Protection
Human Body Model
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Min
Max
4.6
4.6
+150
+70
+115
Unit
V
V
°C
°C
°C
V
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
PCI1
PCI0
FS_A
V
DD
_suspend
REF0
V
SS
_REF
XTAL_IN
XTAL_OUT
V
DD
_REF
SCL
SDA
CPUT0
CPUC0
V
DDA
V
DD
T
STG
T
AMBIENT
T
CASE
ESD Prot
–65
0
2000
V
SS
_PCI
V
DD
_PCI
PCIF
0
/ITP
_
EN
PCIF1
PCIF2
V
DD_
48
USB48MHz
V
SS_
48
DOT_96
DOT_96#
V
DD
_CPU
CPUT1
CPUC1
V
TT
_P
WRGD#
/
P
WRDWN
SRCT1
SRCC1
TEST MODE SELECT
(1)
If TEST_SEL sampled above 2V at V
TT
_P
WRGD
active LOW
Pin38
(test_mode)
1
0
CPU
REF/N
Hi-Z
SRC
REF/N
Hi-Z
PCI/F
REF/N
Hi-Z
REF
REF
Hi-Z
DOT96
REF/N
Hi-Z
USB
REF/N
Hi-Z
V
SS
_CPU
I
REF
FS_B/Test_Mode
FS_C/Test _Sel
CPU2_ITP/SRCT7
CPU2_ITP/SRCC7
V
DD
_SRC
V
SS
_SRC
SRCT2
SRCC2
SRCT3
SRCC3
V
DD
_SRC
SRCT6
SRCC6
SRCT5
SRCC5
NOTE:
1. Once test clock operation has been invoked, TEST_MODE pin will select between
the Hi-Z and REF/N.
V
SS_
SATA
SRCT4_SATA
SRCC4_SATA
ITP_EN
ITP_EN
1
0
pin 38
CPUC2_ITP
SRCC7
pin 39
CPUT_ITP
SRCT7
V
DD
_
SATA
V
SS
_SRC
SSOP
TOP VIEW
HW FREQUENCY SELECTION TABLE
FSC, B, A
101
001
011
010
000
100
110
111
CPU
100
133
166
200
266
333
400
Reserve
SRC4_SATA
100
100
100
100
100
100
100
100
SRC[3:1], SCR[7:5]
100
100
100
100
100
100
100
100
2
PCI
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
USB
48
48
48
48
48
48
48
48
DOT
96
96
96
96
96
96
96
96
REF
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
IDTCV115F
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
V
DD
_PCI
V
SS
_PCI
PCI2
PCI3
PCI4
V
SS
_PCI
V
DD
_PCI
PCIF0/ITP_EN
PCIF1
PCIF2
V
DD
_48
USB48
V
SS
_48
DOT_96T
DOT_96C
V
TT
_P
WRGD
#/P
WRDWN
Type
PWR
GND
OUT
OUT
OUT
GND
PWR
I/O
OUT
OUT
PWR
OUT
GND
OUT
OUT
IN
Description
3.3V
GND
PCI clock
PCI clock
PCI clock
GND
3.3V
PCI clock, free running. CPU_2 select (sampled at V
TT
_P
WRGD
# assertion), HIGH = CPU_2.
PCI clock, free running
PCI clock, free running
3.3V
48MHz clock
GND
96MHz 0.7V current mode differential clock output
96MHz 0.7V current mode differential clock output
3.3V LVTTL input is a level-sensitive strobe used to latch the FS_A, FS_B, FS_C/TEST_SEL and
PCIF_0/ITP_EN inputs. After V
TT
_P
WRGD
# assertion, becomes a real-time input for asserting power
down (active high). Internal pull LOW.
Differential Serial reference clock
Differential Serial reference clock
3.3V
GND
Differential Serial reference clock
Differential Serial reference clock
Differential Serial reference clock
Differential Serial reference clock
GND
SATA clock
SATA clock
3.3V
GND
Differential Serial reference clock
Differential Serial reference clock
Differential Serial reference clock
Differential Serial reference clock
3.3V
Selectable CPU or SRC differential clock output. ITP_EN=0 @ V
TT
_P
WRGD
# assertion = SRC_7
Selectable CPU or SRC differential clock output. ITP_EN=0 @ V
TT
_P
WRGD
# assertion = SRC_7
CPU frequency selection. Selects test mode if pulled above 2V when V
TT
_P
WRGD
# is asserted.
CPU frequency selection. In test mode, 1=Hi-Z, 0=REF/N.
Reference current for differential output buffer
GND
Host 0.7V current mode differential clock output
Host 0.7V current mode differential clock output
3.3V
Host 0.7V current mode differential clock output
Host 0.7V current mode differential clock output
SMBus data
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
SRCT1
SRCC1
V
DD
_SRC
V
SS
SRCT2
SRCC2
SRCT3
SRCC3
V
SS
SRCT4_SATA
SRCC4_SATA
V
DD
_SRC
V
SS
_SRC
SRCC5
SRCT5
SRCC6
SRCT6
V
DD
_SRC
CPUC2_ITP/ SRCC7
CPUT2_ITP/ SRCT7
FS_C/Test_Sel
FS_B/ Test_Mode
IREF
V
SS
CPUC1
CPUT1
V
DD
_CPU
CPUC0
CPUT0
SDA
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
GND
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
PWR
OUT
OUT
IN
IN
OUT
GND
OUT
OUT
PWR
OUT
OUT
I/O
3
IDTCV115F
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONT.)
Pin Number
47
48
49
50
51
52
53
54
55
56
Name
SCL
V
DD
_REF
XTAL_OUT
XTAL_IN
V
SS
_REF
REF0
V
DD
_Suspend
FS_A
PCI0
PCI1
Type
IN
PWR
OUT
IN
GND
OUT
PWR
IN
OUT
OUT
Description
SMBus CLK
3.3V
Xtal output
Xtal input
GND
14.318 MHz reference clock output
In the power down mode, supply 3.3V to SM control registers, <1mA. In the normal operation, regular
V
DD
.
CPU frequency selection
PCI clock
PCI clock
SM PROTOCOL
INDEX BLOCK WRITE PROTOCOL
Bit
1
2-9
10
11-18
19
20-27
28
29-36
37
38-45
46
# of bits
1
8
1
8
1
8
1
8
1
8
1
From
Master
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Description
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Nth data byte
Acknowledge
Stop
INDEX BLOCK READ PROTOCOL
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit30-37).
Bit
1
2-9
10
11-18
19
20
21-28
29
30-37
38
39-46
47
48-55
# of bits
1
8
1
8
1
1
8
1
8
1
8
1
8
From
Master
Master
Slave
Master
Slave
Master
Master
Slave
Slave
Master
Slave
Master
Slave
Description
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Repeated Start
D3h
Ack (Acknowledge)
Byte count, N (block read back of N
bytes), Byte 8
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Ack (Acknowledge)
Nth data byte
Not acknowledge
Stop
Master
Slave
Master
INDEX BYTE WRITE
Setting bit[11:18] = starting address, bit[20:27] = 01h.
4
INDEX BYTE READ
Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.
IDTCV115F
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
S.E. CLOCK STRENGTH SELECTION
(PCI, REF, USB48)
Str[1:0]
00
01
10
11
1
0.8
0.6
1.2
PCI
When Byte5 bit6 = 0; otherwise, PCI = SRC frequency/3
PCIS[1:0]
00
01
10
11
PCI
33.33
36.36
40
n/a
S_CNS, S_PNS, H_CNS,H_PNS N
SELECTION
NS[1:0]
00
01
10
11
Standard of Each CPU Mode (Band)
N Selection 1
N Selection 2
Don’t care
SSC MAGNITUDE CONTROL, SMC
SMC[2:0]
000
001
010
011
100
101
110
111
%
OFF
- 0.3
- 0.5
±0.125
±0.25
±0.375
±0.5
±0.4
RESOLUTION
CPU
CPU
CPU
CPU
CPU
CPU
CPU
SRC
= 100MHz mode
= 133MHz mode
= 166MHz mode
= 200MHz mode
= 266MHz mode
= 333MHz mode
= 400MHz mode
(PCI Express)
N Resolution (MHz)
0.666667
0.888889
1.333333
1.333333
2.666667
2.666667
2.666667
0.666667
%
0.67%
0.67%
0.8%
0.67%
1.00%
0.8%
0.67%
0.67%
RESOLUTION FINE TUNE
IB_[1:0]
CPU = 100MHz
CPU = 133MHz
CPU = 166MHz
CPU = 200MHz
CPU = 266MHz
CPU = 333MHz
CPU = 400MHz
mode
mode
mode
mode
mode
mode
mode
00 and 11
No increase
No increase
No increase
No increase
No increase
No increase
No increase
01 (resolution * 1/3)
0.2222 MHz
0.2963MHz
0.4444MHz
0.4444MHz
0.888888MHz
0.888888MHz
0.888888MHz
10 (resolution * 2/3)
0.4444MHz
0.5926MHz
0.8888MHz
0.8888MHz
1.77777MHz
1.77777MHz
1.77777MHz
5
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