MuxOneNAND1G(KFM1G16Q2A-DEBx)
MuxOneNAND2G(KFN2G16Q2A-DEBx)
FLASH MEMORY
KFM1G16Q2A
KFN2G16Q2A
1Gb MuxOneNAND A-die
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
MuxOneNAND
‚ is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be
claimed as the property of their rightful owners.
* Samsung Electronics reserves the right to change products or specification without notice.
1
MuxOneNAND1G(KFM1G16Q2A-DEBx)
MuxOneNAND2G(KFN2G16Q2A-DEBx)
FLASH MEMORY
Revision History
Document Title
MuxOneNAND
Revision History
Revision No. History
0.0
0.1
0.2
1. Initial issue.
1. Corrected Errata
1. Corrected Errata
2. Changed the term BRL to BRWL.
3. Increased NOP from 1 to 2 (per sector).
4. Revised Chap. 3.2 Device Bus Operation .
5. Revised Synchronous Burst Block Read to no-wrap.
1. Corrected Errata
2. Revised tRDYO from 11ns to 9ns.
3. Revised tAAVDH from 7ns to 6ns.
4. Revised tESP value to typ 400us / max 500us.
5. Revised DBS Description.
6. Revised Synchronous Burst Block Read Diagram.
Draft Date
Jul. 26, 2005
Aug. 19, 2005
Oct. 25, 2005
Remark
Advanced
Advanced
Advanced
0.3
Nov. 17, 2005
Advanced
0.4
Dec. 26, 2005
1. Corrected Errata
2. Changed default value of F221h from 60C4h to 40C0h.
Due to this change, synch burst read diagrams are changed to BRWL=4.
3. Revised ECC Register description in Chapter 2.8.21
4. Revised flow charts regarding DBS settings.
(Chapter: 3.4.4, 3.6, 3.9.5, 3.12, 3.12.1, 3.13.1, 3.13.3, 3.13.4, 3.14.1,
3.14.2, 3.14.3, 3.14.4, 3.14.5)
5. Revised Device Bus Operation in Chapter 3.2, CE: L -> low going edge.
6. Revised 3rd address setting condition of Cache Read in Chapter 3.8.
7. Changed tBDH to 2.5ns for 66MHz, 1.5ns for 83MHz in Chapter 5.4.
8. Revised Erase Operation Timing Diagram in Chapter 6.13
9. Added INT auto mode regulation to Synchronous Burst Block Operation.
10. Changed tBA to 11ns for 66MHz in Chapter 5.4.
11. Changed tRDYO to 11ns for 66MHz in Chapter 5.4 and 5.8.
12. Changed tRDYA to 11ns for 66MHz in Chapter 5.4 and 5.8.
13. Changed tRDYS to 4ns for 66MHz in Chapter 5.4 and 5.8.
14. Changed tCES to 4.5ns for 83MHz in Chapter 5.4 and 5.8.
15. Updated DC parameters.
16. Changed INT pin description to DQ-type in Chapter 7.1.
17. Revised Synchronous Burst Block Read description in Chapter 3.9.
18. Revised Synchronous Burst Block Read Timing Diagram and
description in Chapter 6.3 and 6.4.
19. Divided pin connection guide in synchronous mode into
handshaking / non-handshaking mode in Chapter 7.1.1 and 7.1.2
20. Added note that all command based operations only supports
asynchronousoperation in Chapter 3.1
21. Added restriction to synchronous write operation in Chapter 3.10
22. Added new timing diagram ’Start Initial Burst Write’ in Chapter 6.10
Preliminary
2
MuxOneNAND1G(KFM1G16Q2A-DEBx)
MuxOneNAND2G(KFN2G16Q2A-DEBx)
FLASH MEMORY
Revision History
Document Title
MuxOneNAND
Revision History
1.0
Mar. 22, 2006
1. Corrected errata.
2. Chapter 1.5 & 2.8.19 & 3.7.2.3 :Revised description related to HF.
3. Chapter 2.4 : Modified ’INT’ description.
4. Chapter 2.8.13 & 3.9 & 6.3 : Revised the restriction regarding FPC set-
ting.
5. Chapter 2.8.16 & 2.8.17 : Added a comment about FSA, BSA & BSC set-
ting, in case of Synchronous Burst Block.
6. Chapter 2.8.25 : Added a comment about DBS, DFS setting before read-
ing its status.
7. Chapter 3.8 : Moved DBS setting step up in the flow chart.
8. Chapter 3.9 : Added a commnet about the limitation of address when
accessing DataRAM in case of Synchronous Burst Block Read.
9. Chapter 3.12 : Added a comment about the restriction of Copy-back oper-
ation.
10. Chapter 3.14 : Modified user area size in OTP block.
11. Chapter 4.3 : Revised 3 parameter values on DDP.
(Active Burst Read Current, Active Burst Write Current and Active Asyn-
chronous Write Current)
12. Chapter 5.4 & 5.7 & 5.8 : Added tCEZ parameter on the table.
13. Chapter 6.13 : Revised Block Erase operation timing.
14. Chapter 7.1 & 7.1.1 & 7.1.2 : Added and modified explanation about INT
behavior and pin description.
15. Chapter 7.1.3 : Revised t
r
, t
f
and I
BUSY
values based on 73nm technol-
ogy.
Final
1.1
Apr.18, 2006
1. Correctied errata.
2. Chapter 1.4 : Modified design technology description and added ’1st
block OTP’ after ’User-controlled One Time Programmable(OTP) area’.
3. Chapter 2.8.3 : Eliminated ’Top boot’ option.
4. Chapter 2.8.18 : Added acceptible command during busy on Unlock,
Lock, Lock-tight, All block unlock and Erase suspend operation.
5. Chapter 2.8.18 : Revised Note 2).
6. Chapter 2.8.25 : Eliminated ’bit’ column from table.
7. Chapter 3.1 : Eliminated ’read data from buffer’ and ’write data to buffer’
contents.
8. Chapter 3.3 : Revised default value on Start Block Address with hot reset.
9. Chapter 3.5 : Revised POR level into 1.5V and resetting guidance.
10. Chapter 3.7.2 : Revised ’Continuous Burst’ of ’Burst Address Sequence’
on table.
11. Chapter 3.13.2 : Eliminated the expression ’suspended’ on Case 2.
12. Chapter 3.14.1 : Revised Note 1 on OTP load flow chart.
13. Chapter 5.4 : Revised tBDH parameter value into 2ns with 83Mhz.
14. Chapter 5.6 : Revised symbol of tREADY1 into BootRAM.
15. Chapter 5.10 : Revised tWB table.
16. Chapter 5.11 : Revised tINTL table and its value.
17. Chapter 6.11 : Revsied tRD into tRD1 or tRD2.
18. Chapter 6.12 : Revsied tPGM into tPGM1 or tPGM2.
19. Chapter 6.13 : Revsied tBERS into tBERS1.
20. Chapter 6.18 : Revised timing diagram.
Final
3
MuxOneNAND1G(KFM1G16Q2A-DEBx)
MuxOneNAND2G(KFN2G16Q2A-DEBx)
FLASH MEMORY
Revision History
Document Title
OneNAND
Revision History
Revision No.
1.2
1. Chapter 2.8.12 & 2.8.16 & 3.8 : Added a. comment about FSA & FCSA
setting on Cache Read Operation
2. Chapter 3.9.5 : Corrected flow chart
3. Chapter 5.8 : Revised tWDH values.
Draft Date
July. 4, 2006
Remark
Final
4
MuxOneNAND1G(KFM1G16Q2A-DEBx)
MuxOneNAND2G(KFN2G16Q2A-DEBx)
FLASH MEMORY
1.0
INTRODUCTION
This specification contains information about the Samsung Electronics Company MuxOneNAND ‚ Flash memory product family.
Section 1.0 includes a general overview, revision history, and product ordering information.
Section 2.0 describes the MuxOneNAND device. Section 3.0 provides information about device operation. Electrical specifications
and timing waveforms are in Sections 4.0 though 6.0. Section 7.0 provides additional application and technical notes pertaining to
use of the MuxOneNAND. Package dimensions are found in Section 8.0
Density
1Gb
2Gb
Part No.
KFM1G16Q2A-DEBx
KFN2G16Q2A-DEBx
V
CC
(core & IO)
1.8V(1.7V~1.95V)
1.8V(1.7V~1.95V)
Temperature
Extended
Extended
PKG
63FBGA(LF)
63FBGA(LF)
1.1
Flash Product Type Selector
Samsung offers a variety of Flash solutions including NAND Flash, MuxOneNAND and NOR Flash. Samsung offers Flash products
both component and a variety of card formats including RS-MMC, MMC, CompactFlash, and SmartMedia.
To determine which Samsung Flash product solution is best for your application, refer the product selector chart.
Samsung Flash Products
Application Requires
Fast Random Read
Fast Sequential Read
Fast Write/Program
Multi Block Erase
Erase Suspend/Resume
Copyback
Lock/Unlock/Lock-Tight
ECC
Scalability
External (Hardware/Software)
Internal
X
(EDC)
(ECC)
(Max 64 Blocks)
NAND
MuxOneNAND
NOR
5
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