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72T55268L6-7BBI: 产品描述PBGA-324, Tray; 产品类别存储存储; 文件大小574KB，共65页; 制造商IDT (Integrated Device Technology)

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72T55268L6-7BBI概述

PBGA-324, Tray

72T55268L6-7BBI规格参数

参数名称	属性值
Brand Name	Integrated Device Technology
是否无铅	含铅
是否Rohs认证	不符合
零件包装代码	PBGA
包装说明	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
针数	324
制造商包装代码	BB324
Reach Compliance Code	not_compliant
ECCN代码	EAR99
最长访问时间	3.8 ns
最大时钟频率 (fCLK)	200 MHz
周期时间	6.7 ns
JESD-30 代码	S-PBGA-B324
JESD-609代码	e0
长度	19 mm
内存密度	5242880 bit
内存集成电路类型	OTHER FIFO
内存宽度	40
湿度敏感等级	3
功能数量	1
端子数量	324
字数	131072 words
字数代码	128000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	128KX40
可输出	YES
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装等效代码	BGA324,18X18,40
封装形状	SQUARE
封装形式	GRID ARRAY
并行/串行	PARALLEL
峰值回流温度（摄氏度）	225
电源	2.5 V
认证状态	Not Qualified
座面最大高度	1.97 mm
最大压摆率	0.33 mA
最大供电电压 (Vsup)	2.625 V
最小供电电压 (Vsup)	2.375 V
标称供电电压 (Vsup)	2.5 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	Tin/Lead (Sn63Pb37)
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	19 mm
Base Number Matches	1

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2.5V QUADMUX DDR FLOW-CONTROL DEVICE

WITH MUX/DEMUX/BROADCAST FUNCTIONS

8,192 x 40 x 4

16,384 x 40 x 4

32,768 x 40 x 4

IDT72T55248

IDT72T55258

IDT72T55268

FEATURES

•

Choose from among the following memory organizations:

IDT72T55248 - 8,192 words, 40-bits/word maximum, 4 Sequential

Queues total

IDT72T55258 - 16,384 words, 40-bits/word maximum, 4 Sequential

Queues total

IDT72T55268 - 32,768 words, 40-bits/word maximum, 4 Sequential

Queues total

User Selectable Mux / Demux / Broadcast Write Modes

Mux Mode offers 4:1 architecture

- Five discrete clock domains, four write clocks and one read clock

- Four separate write ports, writes data to four independent Queues

- One single read port, capable of reading from any four Queues

- Selectable single or double data rate (SDR/DDR) on read and write

ports

- 10-bit wide write ports in single data rate, doubles internally in double

data rate

- 40-bit wide read port, doubles internally in double data rate,

selectable between the four independent Queues

- Bus Matching on the Read Port x10/x20/x40 (SDR/DDR)

- Fully independent status flags for every Queue

- Composite Empty/Output Ready Flag monitors currently selected

Queue

- Dedicated partial reset for every Queue

•

Demux Mode offers 1:4 architecture

- Five discrete clock domains, one write clock and four read clocks

- Four separate read ports, read data from four independent Queues

- One single write port, capable of writing to any four Queues

- Selectable single or double data rate on read and write ports

- 10-bit wide read ports in single data rate, doubles internally in double

data rate

- 40-bit wide write port, doubles internally in double data rate,

selectable between the four independent Queues

- Bus Matching on the Write Port x10/x20/x40 (SDR/DDR)

- Fully independent status flags for every Queue

- Composite Full/Input Ready Flag monitors currently selected Queue

- Dedicated partial reset for every Queue

Broadcast Write Mode offers, 1:4 architecture (with simultaneous

writes to all Queues)

- Five discrete clock domains, one write clock and four read clocks

- Four separate read ports, read data from four independent Queues

- One single write port, writes to all four independent Queues

simultaneously

- 10-bit wide read ports in single data rate, doubles internally in double

data rate

- 40-bit wide write port, doubles internally in double data rate

- Selectable single or double data rate on read and write ports

- Bus-Matching on the write port x10/x20/x40 (SDR/DDR)

FUNCTIONAL BLOCK DIAGRAMS

Mux Mode

Read Control

Queue 0

Data In

WCLK0

WEN0

WCS0

8,192 x 40

16,384 x40

32,768 x 40

Queue 0

8,192 x 40

16,384 x40

32,768 x 40

Queue 1

8,192 x 40

16,384 x40

32,768 x 40

Queue 2

8,192 x 40

16,384 x40

32,768 x 40

RCLK0

REN0

RCS0

OE0

OS[1:0]

D[9:0]

WCLK1

WEN1

WCS1

Queue 1

Data In D[19:10]

x10,x20,x40

Queue 2

Data In D[29:20]

WCLK2

WEN2

WCS2

Data Out

Q[39:0]

Queue 3

Data In D[39:30]

WCLK3

WEN3

WCS3

FF0/IR0

PAF0

FF1/IR1

PAF1

FF2/ IR2

PAF2

FF3/IR3

PAF3

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc

(See next pages for Demux and Broadcast modes)

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

Read Port

Flag Outputs

Queue 3

EF0/OR0

PAE0

EF1/OR1

PAE1

EF2/OR2

PAE2

EF3/OR3

PAE3

CEF/COR

Write Port

Flag Outputs

6157 drw01

FEBRUARY 2009

DSC-6157/5

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

Table of Contents

Features ...................................................................................................................................................................................................................... 1,4

Description ...................................................................................................................................................................................................................... 6

Pin Configuration ............................................................................................................................................................................................................. 8

Pin Descriptions .......................................................................................................................................................................................................... 9-13

Device Characteristics ................................................................................................................................................................................................... 15

DC Electrical Characteristics .......................................................................................................................................................................................... 16

AC Electrical Characteristics ........................................................................................................................................................................................... 17

AC Test Conditions ........................................................................................................................................................................................................ 18

Functional Description .............................................................................................................................................................................................. 20-29

Signal Descriptions ................................................................................................................................................................................................... 30-33

JTAG Timing Specifications ....................................................................................................................................................................................... 36-40

List of Tables

Table 1 — Device Configuration .................................................................................................................................................................................... 20

Table 2 — Default Programmable Flag Offsets ................................................................................................................................................................ 20

Table 3 — Status Flags for IDT Standard mode ............................................................................................................................................................. 23

Table 4 — Status Flags for FWFT mode ........................................................................................................................................................................ 23

Table 5 — I/O Voltage Level Associations ....................................................................................................................................................................... 24

Table 6 — TSKEW Measurement .................................................................................................................................................................................. 34

FEBRUARY 01, 2009

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

List of Figures

Figure 1. QuadMux Block Diagram .................................................................................................................................................................................. 7

Figure 2a. AC Test Load ................................................................................................................................................................................................ 18

Figure 2b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 18

Figure 3. Programmable Flag Offset Programming Methods ........................................................................................................................................... 21

Figure 4. Offset Registers Serial Bit Sequence ................................................................................................................................................................ 22

Figure 5. Bus-Matching Byte Arrangement (Mux, DeMux and Broadcast Mode) ....................................................................................................... 25-27

Figure 6. Echo Read Clock and Data Output Relationship .............................................................................................................................................. 35

Figure 7. Standard JTAG Timing ................................................................................................................................................................................... 36

Figure 8. JTAG Architecture ........................................................................................................................................................................................... 37

Figure 9. TAP Controller State Diagram ......................................................................................................................................................................... 38

Figure 10. Master Reset ................................................................................................................................................................................................ 41

Figure 11. Partial Reset for Mux mode ........................................................................................................................................................................... 42

Figure 12. Partial Reset for Demux mode ...................................................................................................................................................................... 43

Figure 13. Partial Reset for Broadcast mode .................................................................................................................................................................. 44

Figure 14. Write Cycle and Full Flag Timing (Mux mode, IDT Standard mode, SDR to SDR) x10 In to x40 Out ............................................................. 45

Figure 15. Write Cycle and Full Flag Timing (Broadcast Write mode, IDT Standard mode, SDR to SDR) x10 In to x10 Out ............................................ 46

Figure 16. Write Cycle and Full Flag Timing (Demux mode, IDT Standard mode, SDR to SDR) x10 In to x10 Out ......................................................... 47

Figure 17. Write Timing (Mux mode, FWFT mode, SDR to SDR) x10 In to x10 Out ........................................................................................................ 48

Figure 18. Write Timing (Broadcast Write mode, FWFT mode, SDR to SDR) x10 In to x10 Out ....................................................................................... 49

Figure 19. Write Timing (Demux mode, FWFT mode, SDR to SDR) x10 In to x10 Out ................................................................................................... 50

Figure 20. Read Cycle, Empty Flag and First Word Latency (Mux mode, IDT Standard mode, SDR to SDR) x10 In to x40 Out ..................................... 51

Figure 21. Read Timing (Broadcast Write mode, FWFT mode, SDR to SDR) x10 In to x10 Out ...................................................................................... 52

Figure 22. Read Timing (Mux mode, FWFT mode, SDR to SDR) x10 In to x10 Out ....................................................................................................... 53

Figure 23. Read Timing (Demux mode, FWFT mode, SDR to SDR) x20 In to x10 Out .................................................................................................. 53

Figure 24. Read Cycle, Empty Flag and First Word Latency (Demux mode, IDT Standard mode, SDR to SDR) x20 In to x10 Out ................................. 54

Figure 25. Read Cycle, Empty Flag and First Word Latency (Broadcast Write mode, IDT Standard mode, SDR to SDR) x40 In to x10 Out .................... 55

Figure 26. Composite Empty Flag (Mux mode, IDT Standard mode, SDR to SDR) x10 In to x40 Out ............................................................................. 56

Figure 27. Composite Output Ready Flag (Mux mode, FWFT mode, SDR to SDR) x10 In to x40 Out ............................................................................ 56

Figure 28. Composite Full Flag (Demux mode, IDT Standard mode, SDR to SDR) x20 In to x10 Out ............................................................................ 57

Figure 29. Composite Input Ready Flag (Demux mode, FWFT mode, SDR to SDR) x20 In to x10 Out .......................................................................... 57

Figure 30. Echo Read Clock and Read Enable Operation (Mux/Demux/Broadcast mode, IDT Standard mode, DDR to DDR) x10 In to x10 Out ........... 58

Figure 31. Echo RCLK and Echo Read Enable Operation (Mux/Demux/Broadcast mode, FWFT mode, SDR to SDR) .................................................. 59

Figure 32. Echo Read Clock and Read Enable Operation (Mux/Demux/Broadcast mode, IDT Standard mode, SDR to SDR) x10 In to x10 Out ........... 60

Figure 33. Loading of Programmable Flag Registers (IDT Standard and FWFT modes) ................................................................................................ 61

Figure 34. Reading of Programmable Flag Registers (IDT Standard and FWFT modes) ................................................................................................ 61

Figure 35. Synchronous Programmable Almost-Full Flag Timing (see page for details) ................................................................................................... 62

Figure 36. Synchronous Programmable Almost-Empty Flag Timing (see page for details) ............................................................................................... 62

Figure 37. Asynchronous Programmable Almost-Full Flag Timing (see page for details) ................................................................................................ 63

Figure 38. Asynchronous Programmable Almost-Empty Flag Timing (see page for details) ............................................................................................ 63

Figure 39. Power Down Operation ................................................................................................................................................................................ 64

FEBRUARY 01, 2009

72T55268L6-7BBI相似产品对比

	72T55268L6-7BBI	72T55258L6-7BBI	72T55258L5BB	72T55268L6-7BB	72T55248L5BB	72T55248L6-7BB	72T55248L6-7BBI	72T55268L5BB	72T55258L6-7BB
描述	PBGA-324, Tray	PBGA-324, Tray	PBGA-324, Tray	PBGA-324, Tray	PBGA-324, Tray	PBGA-324, Tray	PBGA-324, Tray	PBGA-324, Tray	PBGA-324, Tray
Brand Name	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology
是否无铅	含铅	含铅	含铅	含铅	含铅	含铅	含铅	含铅	含铅
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合
零件包装代码	PBGA	PBGA	PBGA	PBGA	PBGA	PBGA	PBGA	PBGA	PBGA
包装说明	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
针数	324	324	324	324	324	324	324	324	324
制造商包装代码	BB324	BB324	BB324	BB324	BB324	BB324	BB324	BB324	BB324
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
最长访问时间	3.8 ns	3.8 ns	3.6 ns	3.8 ns	3.6 ns	3.8 ns	3.8 ns	3.6 ns	3.8 ns
最大时钟频率 (fCLK)	200 MHz	200 MHz	200 MHz	200 MHz	200 MHz	200 MHz	200 MHz	200 MHz	200 MHz
周期时间	6.7 ns	6.7 ns	5 ns	6.7 ns	5 ns	6.7 ns	6.7 ns	5 ns	6.7 ns
JESD-30 代码	S-PBGA-B324	S-PBGA-B324	S-PBGA-B324	S-PBGA-B324	S-PBGA-B324	S-PBGA-B324	S-PBGA-B324	S-PBGA-B324	S-PBGA-B324
JESD-609代码	e0	e0	e0	e0	e0	e0	e0	e0	e0
长度	19 mm	19 mm	19 mm	19 mm	19 mm	19 mm	19 mm	19 mm	19 mm
内存密度	5242880 bit	2621440 bit	2621440 bit	5242880 bit	1310720 bit	1310720 bit	1310720 bit	5242880 bit	2621440 bit
内存集成电路类型	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO
内存宽度	40	40	40	40	40	40	40	40	40
湿度敏感等级	3	3	3	3	3	3	3	3	3
功能数量	1	1	1	1	1	1	1	1	1
端子数量	324	324	324	324	324	324	324	324	324
字数	131072 words	65536 words	65536 words	131072 words	32768 words	32768 words	32768 words	131072 words	65536 words
字数代码	128000	64000	64000	128000	32000	32000	32000	128000	64000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	85 °C	85 °C	70 °C	70 °C	70 °C	70 °C	85 °C	70 °C	70 °C
组织	128KX40	64KX40	64KX40	128KX40	32KX40	32KX40	32KX40	128KX40	64KX40
可输出	YES	YES	YES	YES	YES	YES	YES	YES	YES
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
封装等效代码	BGA324,18X18,40	BGA324,18X18,40	BGA324,18X18,40	BGA324,18X18,40	BGA324,18X18,40	BGA324,18X18,40	BGA324,18X18,40	BGA324,18X18,40	BGA324,18X18,40
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
峰值回流温度（摄氏度）	225	225	225	225	225	225	225	225	225
电源	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.97 mm	1.97 mm	1.97 mm	1.97 mm	1.97 mm	1.97 mm	1.97 mm	1.97 mm	1.97 mm
最大压摆率	0.33 mA	0.33 mA	0.33 mA	0.33 mA	0.33 mA	0.33 mA	0.33 mA	0.33 mA	0.33 mA
最大供电电压 (Vsup)	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V
最小供电电压 (Vsup)	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V
标称供电电压 (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
端子面层	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)
端子形式	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
端子节距	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
宽度	19 mm	19 mm	19 mm	19 mm	19 mm	19 mm	19 mm	19 mm	19 mm
Base Number Matches	1	1	1	1	1	1	1	-	-
厂商名称	-	IDT (Integrated Device Technology)	-	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)

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