Preliminary Information
CAT1021, CAT1022, CAT1023
Supervisory Circuits with I
2
C Serial 2K CMOS EEPROM, Manual Reset
and Watchdog Timer
FEATURES
s
Precision power supply voltage monitor
s
Built-in inadvertent write protection
— 5V, 3.3V and 3V systems
— Five threshold voltage options
s
Watchdog timer
s
Active high or low reset
— WP pin (CAT1021)
s
1,000,000 Program/Erase cycles
s
Manual reset input
s
100 year data retention
s
8-pin DIP, SOIC, TSSOP, TDFN (MSOP
— Valid reset guaranteed at V
CC
=1V
s
400kHz I
2
C bus
s
2.7V to 5.5V operation
s
Low power CMOS technology
s
16-Byte page write buffer
(3x4.9mm) & 3x3mm foot prints) or MSOP
packages
— TDFN max height is 0.8mm
s
Automotive, extended automotive and
industrial temperature ranges
DESCRIPTION
The CAT1021, CAT1022 and CAT1023 are complete
memory and supervisory solutions for microcontroller-
based systems. A 2kbit serial EEPROM memory and a
system power supervisor with brown-out protection are
integrated together in low power CMOS technology.
Memory interface is via a 400kHz I
2
C bus.
The CAT1021 and CAT1023 provide a precision V
CC
sense circuit and two open drain outputs: one (RESET)
drives high and the other (RESET) drives low whenever
V
CC
falls below the reset threshold voltage. The CAT1021
also has a Write Protect input (WP). Write operations
are disabled if WP is connected to a logic high.
The CAT1022 has a
RESET
output and does not have
a Write Protect input.
All supervisors have a 1.6 second watchdog timer circuit
that resets a system to a known state if software or a
hardware glitch halts or “hangs” the system. For the
CAT1021 and CAT1022, the watchdog timer monitors
the SDA signal. The CAT1023 has a separate watchdog
timer interrupt input pin, WDI.
The power supply monitor and reset circuit protect memory
and system controllers during power up/down and against
brownout conditions. Five reset threshold voltages support
5V, 3.3V and 3V systems. If power supply voltages are out
of tolerance reset signals become active, preventing the
system microcontroller, ASIC or peripherals from operating.
Reset signals become inactive typically 200 ms after the
supply voltage exceeds the reset threshold level. With both
active high and low reset signals, interface to microcontrollers
and other ICs is simple. In addition, the
RESET
pin or a
separate input,
MR,
can be used as an input for push-button
manual reset capability.
The on-chip, 2k EEPROM memory features a 16-byte page.
In addition, hardware data protection is provided by a V
CC
sense circuit that prevents writes to memory whenever V
CC
falls below the reset threshold or until V
CC
reaches the reset
threshold during power up.
Available packages include an 8-pin DIP and surface mount
8-pin SO, 8-pin TSSOP, 8-pin TDFN and 8-pin MSOP
packages. The TDFN package thickness is 0.8mm maximum.
TDFN footprint options are 3x3mm or 3x4.9mm (MSOP pad
layout).
© 2003 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 3009, Rev. E
CAT1021, CAT1022, CAT1023
Preliminary Information
BLOCK DIAGRAM
EXTERNAL LOAD
DOUT
ACK
VCC
VSS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SENSE AMPS
SHIFT REGISTERS
Threshold Voltage Options
Part Dash Minimum
Number Threshold
-45
-42
-30
-28
-25
4.50
4.25
3.00
2.85
2.55
Maximum
Threshold
4.75
4.50
3.15
3.00
2.70
SDA
START/STOP
LOGIC
2kbit
EEPROM
XDEC
WP
(CAT1021)
CONTROL
LOGIC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
RESET Controller
Precision
MR
Vcc Monitor
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
SCL
RESET
(CAT1021/23)
RESET
WDI
(CAT1023)
PIN CONFIGURATION
(Bottom View)
TDFN Package: 3mm x 4.9mm
0.8mm maximum height - (RD2)
VCC
RESET
SCL
SDA
8
7
1
2
(Bottom View)
TDFN Package: 3mm x 3mm
0.8mm maximum height - (RD4)
VCC
RESET
SCL
SDA
8
7
1
2
MR
1
RESET
2
WP 3
VSS 4
8 VCC
CAT1021
7 RESET
6 SCL
5 SDA
MR
RESET
WP
VSS
MR
RESET
WP
VSS
CAT1021
6
5
CAT1021
6
5
3
4
3
4
MR
1
RESET
2
NC 3
VSS 4
CAT1022
8 VCC
7 NC
6 SCL
5 SDA
VCC
NC
SCL
SDA
8
7
1
2
MR
RESET
NC
VSS
VCC
NC
SCL
SDA
8
7
1
2
MR
RESET
NC
VSS
CAT1022
6
5
3
4
CAT1022
6
5
3
4
MR
1
RESET
2
RESET 3
VSS 4
CAT1023
8 VCC
7 WDI
6 SCL
5 SDA
VCC
WDI
SCL
SDA
8
7
1
2
MR
RESET
RESET
VSS
VCC
8
WDI
7
SCL
6
SDA
5
1
MR
2
RESET
CAT1023
6
5
3
4
CAT1023
3
RESET
4
V
SS
Doc. No. 3009, Rev. E
2
Preliminary Information
CAT1021, CAT1022, CAT1023
MANUAL RESET INPUT
MR:
Manual Reset input is a debounced input that can be
connected to an external source for Manual Reset.
Pulling the MR input low will generate a Reset condition.
Reset outputs are active while
MR
input is low and for
the reset timeout period after
MR
returns to high. The
input has an internal pull up resistor.
WP (CAT1021 Only):
WRITE PROTECT INPUT
When WP input is tied to V
SS
or left unconnected write
operations to the entire array are allowed. When tied to
V
CC
, the entire array is protected. This input has an
internal pull down resistor.
WDI (CAT1023 Only):
WATCHDOG TIMER INTERRUPT
Watchdog Timer Interrupt Input is used to reset the
watchdog timer. If a transition from high to low or low to
high does not occur every 1.6 seconds, the RESET
outputs will be driven active.
OPERATING TEMPERATURE RANGE
Industrial
Automotive
Extended
-40˚C to 85˚C
-40˚C to 105˚C
-40˚C to 125˚C
PIN DESCRIPTION
RESET/RESET
RESET:
RESET OUTPUTS
RESET
(RESET CAT1021/23 Only)
These are open drain pins and
RESET
can be used as a
manual reset trigger input. By forcing a reset condition on
the pin the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull-down
resistor, and the
RESET
pin must be connected through a
pull-up resistor.
SDA:
SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire-ORed with other open drain
or open collector outputs.
SCL:
SERIAL CLOCK
Serial clock input.
PIN FUNCTIONS
Pin Name
NC
RESET
V
SS
SDA
SCL
RESET
V
CC
WP
MR
WDI
Function
No Connect
Active Low Reset Input/Output
Ground
Serial Data/Address
Clock Input
Active High Reset Output (CAT1021/23)
Power Supply
Write Protect (CAT1021 only)
Manual Reset Input
Watchdog Timer Interrupt (CAT1023)
CAT10XX FAMILY OVERVIEW
Device
Manual
Reset
Input Pin
Watchdog
Watchdog
Monitor
Pin
SDA
SDA
WDI
Write
Protection
Pin
Independent
Auxiliary
Voltage Sense
RESET: Active
High and LOW
EEPROM
CAT1021
CAT1022
CAT1023
CAT1024
CAT1025
CAT1026
CAT1027
2k
2k
2k
2k
2k
2k
WDI
2k
For Supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163
data sheets.
3
Doc No. 3009, Rev. E
CAT1021, CAT1022, CAT1023
Preliminary Information
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
Note:
(1) The minimum DC input voltage is –0.5V. During transitions,
inputs may undershoot to
–2.0V for periods of less than 20 ns. Maximum DC voltage on
output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V
for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than
one output shorted at a time.
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to Ground
(1)
............ –2.0V to +V
CC
+2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.7V to +5.5V and over the recommended temperature conditions unless otherwise specified.
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
SB
V
IL3
V
IH3
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Power Supply Current (Write)
Power Supply Current (Read)
Standby Current
Input Low Voltage
Input High Voltage
Output Low Voltage
(SDA,
RESET
)
Output High Voltage
(RESET)
I
OL
= 3mA
V
CC
= 2.7V
I
OH
= -0.4mA
V
CC
= 2.7V
CAT102x-45
(V
CC
= 5V)
CAT102x-42
(V
CC
= 5V)
V
TH
Reset Threshold
CAT102x-30
(V
CC
= 3.3V)
CAT102x-28
(V
CC
= 3.3V)
CAT102x-25
(V
CC
= 3V)
V
RVALID
V
RT1
Reset Output Valid V
CC
Voltage
Reset Threshold Hysteresis
Vcc -
0.75
4.50
4.25
3.00
2.85
2.55
1.00
15
4.75
4.50
3.15
3.00
2.70
V
mV
V
Test Conditions
V
IN
= GND to Vcc
V
IN
= GND to Vcc
f
SCL
= 400kHz
V
CC
= 5.5V
f
SCL
= 400kHz
V
CC
= 5.5V
Vcc = 5.5V,
V
IN
= GND or Vcc
-0.5
0.7 x Vcc
Min
-2
-10
Typ
Max
10
10
3
1
60
0.3 x Vcc
Vcc + 0.5
0.4
Units
µA
µA
mA
mA
µA
V
V
V
V
Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
2. Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to V
CC
+ 1V.
3. V
IL
min and V
IH
max are reference values only and are not tested.
Doc. No. 3009, Rev. E
4
Preliminary Information
CAT1021, CAT1022, CAT1023
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
OUT(1)
C
IN(1)
Test
Output Capacitance
Input Capacitance
Test Conditions
V
OUT
= 0V
V
IN
= 0V
Max
8
6
Units
pF
pF
A.C. CHARACTERISTICS
V
CC
= 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle
2
Symbol
f
SCL
t
SP
t
LOW
t
HIGH
t
R1
t
F1
t
HD;STA
t
SU;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
AA
t
DH
t
BUF1
t
WC3
Parameter
Clock Frequency
Input Filter Spike
Suppression (SDA, SCL)
Clock Low Period
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time
(for a Repeated Start)
Data Input Hold Time
Data Input Setup Time
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
Time the Bus must be Free Before a
New Transmission Can Start
Write Cycle Time (Byte or Page)
50
1.3
5
0.6
0.6
0
100
0.6
900
1.3
0.6
300
300
Min
Max
400
100
Units
kHz
ns
µs
µs
ns
ns
µs
µs
ns
ns
µs
ns
ns
µs
ms
Notes:
1. This parameter is characterized initially and after a design or process change that affects
the parameter. Not 100% tested.
2. Test Conditions according to “AC Test Conditions” table.
3. The write cycle time is the time from a valid stop condition of a write sequence to the end of
the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled,
SDA is allowed to remain high and the device does not respond to its slave address.
5
Doc No. 3009, Rev. E
为我们提建议&公告
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
